IAR Systems® proudly presented support for 64-bit RISC-V cores in the professional development toolchain IAR Embedded Workbench® for RISC-V. With this extended core support, IAR Systems continues to be at the forefront of providing professional development solutions for RISC-V.
IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain with everything embedded developers need to be integrated into one single IDE, including integrated code analysis tools ensuring code quality. Through its excellent optimization technology, IAR Embedded Workbench for RISC-V helps developers ensure the application fits the required needs and optimize the utilization of onboard memory. Version 3.10 of IAR Embedded Workbench for RISC-V supports RV64 RISC-V cores, including several RV64 devices from Andes, Codasip, Microchip, Nuclei, and SiFive further extending the toolchain’s wide support for available RISC-V devices. In addition, symmetric multicore processing (SMP) is now supported, enabling high-performance debugging of multicore RISC-V devices.
“64-bit support is an important milestone for our investment in the RISC-V technology and ecosystem,” commented Anders Holmberg, CTO, IAR Systems. “RISC-V technology adoption and interest continue to grow, especially in the Asia Pacific region, and we are committed to staying in the forefront when it comes to professional development solutions for building high-quality embedded applications across all industries.”