Solution Targets Multiple Apps Needing Additional High-Speed Extension of FPGAs, Up to 100x Performance of DRAM Random Access Rate
MoSys, Inc. announced the availability of its Cheetah Development Kit featuring an integrated MoSys®BE-3 or PHE Device and Virtex UltraScale + VU9P FPGA. The new development kit provides an integrated Xilinx FPGA and a tightly coupled low latency 1Gb MoSys BE-3 or BLAZAR PHE (Programmable HyperSpeed Engine or PHE) that enables rapid implementation of any algorithms that are benefited by offloading them from the FPGA.
“The Cheetah card offers users the ability to offload functions and algorithms into the PHE, which frees up resources in the FPGA that are better suited to higher priority functions,” stated Michael Miller, MoSys CTO. “By enabling designers to add system functionality, users can tailor a solution and provide a 10x to 100x performance improvement over traditional FPGA implementations.”
The Cheetah card is also capable of supporting user applications looking to replace multiple QDR devices with a single MoSys 1Gb high-speed random-access memory (which allows up to 5G accesses into and out of the single device). The card includes a MoSys BE-3 or PHE and supports all Xilinx VCU1525 applications. It is a dual Slot PCIe form factor (Full Height and Length), with the MoSys BE3 or PHE directly attached to the Virtex UltraScale+ SerDes. There are 16 lanes of GTY SERDES connected to the PHE that provide up to 400Gbps full duplex bandwidth.
MoSys recently announced its Packet Classification and Graph Memory Platform on its new Software Accelerator Product Line. The Cheetah card is supporting hardware for this platform and the PHE version with 32 RISC cores has been shown at multiple trade shows, executing a high-performance, TCAM-alternative function.