PCI-SIG has expanded its technology’s low power capabilities with the introduction of L1 sub-states, Quarter-Swing technology, the M-PCIe specification, as well as new form factors to bring the benefits of PCIe architecture to low power and battery-based devices.
BY AL YANES, PCI-SIG
There are a number of industry trends that are driving the “data domination.” According to Gartner in its report “Predicts 2015: The Internet of Things,” the Internet of Things (IoT) industry is growing at a rapid pace. Gartner projects that there will be 4.9 billion connected IoT devices by the end of 2015, up 30 percent from 2014, and 25 billion connected devices by 2020.
On the mobile front, data on the mobile network is continuing to explode, driven by the growth in mobile video, the plethora of smartphones in the market, and subscribers’ demand for access to their content anytime, anywhere. According to the annual “Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update 2014-2019 White Paper,” global mobile data traffic will increase nearly tenfold between 2014 and 2019, growing at a compound annual growth rate of 57 percent during this time period. Almost 75 percent of this global mobile data traffic will be mobile video by 2019.
This data domination, attributed to the growth of IoT and the mobile data explosion, is driving demand for both faster data rates and for more power-efficient devices. PCI Express (PCIe) technology is well-known in the industry and has long been the interconnect of choice for servers, computers, networking and more as it delivers a low cost, high performance, ubiquitous and robust interface for the computing industry. However, what is less well-known to date is that PCIe is also suitable for mobile and battery-powered devices that require low power and high performance I/O technology.
PCI-SIG, comprised of nearly 800 member companies around the world, is the consortium that owns and manages PCI specifications as open industry standards. From the beginning, PCI-SIG had designed its PCIe architecture with low power features to support adoption in multiple applications from SoCs to high-performance servers. It has recently added additional low power features to maintain its leadership in power efficiency and to meet the demands of new market segments such as IoT and mobile. The PCIe specification’s low power features include L1 Sub-states, Half-swing and Quarter-Swing and the M-PCIe specification.
The PCI Express Power Management specification defines link power management states that a PCI Express physical link is permitted to enter in response to either software driven device-state (D-state) transitions or active state link power management activities.
Central to this is Active State Power Management (ASPM), an autonomous hardware-based, active state mechanism that enables power savings even when the connected components are in the D0 state. After a period of idle link time an ASPM physical-layer protocol places the idle link into a lower power state. Once in a lower power state, transitions to the fully operative link state are triggered by traffic appearing on either side of the link.
The defined link states include L0, L0s, L1, L2 and L3 and the power savings increase as the link state transitions from L0 to L3. At L0, full power is on and all clocks are running, while at L3, all power and clocks are shut off. As you can see, the power savings increase as the link state transitions from L0 to L3. However, this approach comes with more latency as the states go back to L0.
While L0 refers to active state with all PCIe transactions and other operations enabled, L0s is a low latency, energy saving standby state. In this mode, all main power supplies, component reference clocks, and components internal PLLs (Phase-Locked Loops) must be active at all times. The Physical Layer provides mechanisms for quick transitions from this state to the L0 state.
The L1 state on the other hand, delivers a higher latency, low power standby state, as compared to L0s. The L1 link state is optimized for maximum power savings at a cost of longer entry and exit latencies. L1 also reduces link power beyond the L0s state for cases where low power is required and longer transition times are acceptable.
In short, the L0s state delivers very low exit latencies in the realm of several hundred nanoseconds for a small power reduction, while the L1 state delivers exit latencies in the order of microseconds, but with greater power reductions.
However, to further maximize power savings, PCI-SIG has introduced optional L1 power management sub-states defined as L1.1 and L1.2. These sub-states can further reduce link power for cases where very low idle power is required.
Devices that leverage PCIe technology and adopt the newly defined L1 Sub-states will achieve significant reduction in idle power consumption, going from consuming tens of milliwatts of power while in an L1 state down to less than 10 microwatts while in L1.2 Sub-states. Table 1 shows one example of the power savings and exit latencies that can be achieved, depending on device manufacturers’ design choices and implementation. By implementing L1 Sub-states, device manufacturers can reduce idle power consumption significantly, but still retain the ability to quickly come out of sleep mode.
Power Sub-states. Note: these are targets; actual power may vary per implementation.
Half-Swing and Quarter-Swing
PCIe applications that are power sensitive, such as mobile applications, can take advantage of reduced power usage by implanting the reduced swing transmitter option. This involves the use of a reduced swing transmit signal with no de-emphasis. The procedure for specifying a channel for the reduced swing transmitter is identical to that used for the full swing transmitter, with the exception that the worst case behavioral Tx characteristics must reflect the reduced swing and lack of de-emphasis.
This reduced swing is known as “Half-Swing,” and it has been a key feature of the PCI Express architecture since the release of the PCIe 1.0 specification. Half-Swing reduces power via the voltage shift from 800 millivolts to 400 millivolts. Typically, the half-swing mode is specified for power sensitive applications where a shorter channel is acceptable. PCI-SIG plans to reduce this power consumption even further with the introduction of the Quarter-Swing feature in the forthcoming PCIe 4.0 specification, with a target of 200 millivolts. While all PCI Express device Transmitters must support full swing signaling, support for reduced swing signaling is optional and it is up to device manufacturers to choose to implement it (Figure 1).
Power Sub-states. Note: these are targets; actual power may vary per implementation.
PCI-SIG’s M-PCIe specification enables PCI Express architecture to operate over the MIPI Alliance M-PHY physical layer, an established industry specification, to enable aggressive power management solutions while retaining all of the existing benefits of the PCIe architecture. The M-PCIe specification provides uncompromised scalable performance while delivering a consistent user experience across multiple mobile platforms.
As seen in Figure 2, a key feature of the M-PCIe specification is that it does not require any major changes to the upper layers of the PCIe protocol stack.
The PCIe architecture delivers power reduction through half-swing and quarter-swing implementations.
Additional key features include:
- Maintaining compatibility with PCIe programming models
- Multi-lane support, support lane configurations as defined in the PCIe specification
- Support for asymmetric link width configurations
- Support for dynamic bandwidth scalability
- Optimized for RFI/EMI
- Enable short channel circuit optimizations
- Support for all MIPI M-PHY high speed gears
- Support for M-PHY TYPE I MODULE only
- Support for MIPI M-PHY LS gear to be utilized for M-PHY parameter initialization
- Support of 8b/10b data encoding
- Support for shared and independent reference clocks
The adaptation of PCIe protocols to operate over the M-PHY physical layer provides the mobile industry with a low-power, scalable solution that enables interoperability and a consistent user experience across multiple devices. The layered architecture of the PCIe I/O technology facilitates the integration of the power-efficient M-PHY with its extensible protocol stack to deliver best-in-class and highly scalable I/O functionality for mobile devices.
New Form Factors Support IoT and Mobile Devices
Power-constrained mobile devices with a low profile, such as smartphones and tablets, also have different form factor requirements. To address this need, PCI-SIG has introduced new form factors to deliver connectivity and expansion for mobile applications.
PCI-SIG’s M.2 Revision 1.0 specification is a next-generation form factor for ultra-light and thin platforms, that increases design flexibility to support high-end performance and enhanced data rates for power-constrained platforms. In addition, it enables the higher integration of functions onto a single form factor module solution.
As a natural progression from the PCIe Mini Card and PCIe Half Mini Card, the smaller M.2 form factor is designed to meet future market requirements for applications in thin mobile platforms, such as tablets, portable gaming devices, smartphones and devices requiring SSDs. Its extensible design provides scalability for multiple technologies and host interfaces, including Wi-Fi, Bluetooth, SSD and WWAN.
The new M.2 specification allows for the manufacture of larger PCBs, maximizing the use of the card space and leaving behind a minimal footprint. M.2 connectors support both single- and double-sided module cards and are available in connectorized or soldered-down forms. The connectorized forms allow single-sided modules for low profile solutions, or dual-sided modules for increased integration within the platform. All soldered-down module cards are single-sided and are intended for use in low profile applications.
The newest addition to the PCI-SIG portfolio is the OCuLink cable form factor specification, released as Revision 1.0 in October 2015. The specification defines small, low-cost passive and active cable form factors for internal and external applications. Internal cables are defined for PCIe-attached storage to facilitate the SATA transition, while external cables are defined to support PCIe I/O expansion and external PCIe-attached storage.
The PCIe OCuLink cable, optimized for the client and mobile market segments, supports up to four PCIe lanes with all cables supporting 8 Gtransfers/s to deliver up to 32 Gbit/s in each direction within a four lane configuration.
PCI-SIG continues to deliver low cost, high performance, low power specifications to meet the interconnect needs of multiple applications, including the emerging IoT and the exploding mobile market sectors. PCI-SIG designed its PCIe architecture from the beginning with low power features to reduce active and idle power consumption. PCIe technology’s flexible lane width configurations and speed selection have always supported low power solutions for desktops, servers and storage devices.