An ongoing and dynamic evolution of technology is adding features to PCIe that make it ever more compatible with the Internet of Things and mobile devices even though the debut of the full new generation is still some time off.
by Tom Williams, Editor-in-Chief
PCI Express, which was one of the few big winners of the long-ago (early 2000s) switched fabric wars, perhaps because it had its origins in the PC architecture, continues to evolve. That evolution is dynamic and ongoing. While PCI Express is currently in its third generation and projected to emerge in a fourth generation around the mid-2016 time frame, it continues to add new functionality along the way. These interim extensions and engineering change notices, when officially released from the PCI-SIG can be adopted, depending on the demands they may make on hardware, by OEMs and will be included in the next generation specification when that is officially released. The next specification, which will be Gen 4, will also include a greatly enhanced data rate.
The PCI Express specifications are created and controlled by the PCI-SIG, which responds to input from its members when they identify and suggest enhancements and modifications. For example, in 2013, the SIG released MPCIe, which enables PCIe to run over the MIPI M-PHY physical layer technology. The MIPI Alliance develops interface specifications for the mobile ecosystem including such things as mobile handsets and now includes tablets, PCs, cameras and medical devices.
The PCI-SIG is a partner organization with the MIPI Alliance. MPCIe is the adaptation layer that allows you to “stitch” the PCIe protocol stack to the MIPI PHY (Figure 1). While it is a very narrow-scoped specification, it is now possible to run PCI Express anywhere there is an M-PHY without changing any protocols. This change, which is useable today, will be integrated into the next version of the PCIe specification. Likewise, there was an engineering change notice for retiming—a rather minor addition—in response to some members’ needs to retime devices to extend the reach of PCIe channels. This too will be integrated into the coming Gen 4 specification.
Figure 1: MPCIe provides normative references between PCIe protocols and the MIPI PHY so that PCIe can run in devices with MIPI communications.
According to Ramin Neshati, PCI-SIG Board Member and Marketing Workgroup Chair, “These are a couple of examples of how the technology dynamically evolves. Before our release a spec, you can add on some of these things.” This is done by people proposing extensions that, when approved, are captured as engineering change notices. Of course, the scope varies. Some can be applied right away while others may depend on revision to devices, which will be defined by the next version of the spec.
The IoT is Already upon Us
It should come as no surprise that the rise of the Internet of Things is having an effect on serial communication technologies and PCI Express is quite naturally in the thick of it. According to Neshati, the PCI-SIG did a study for the adaptation to the IoT looking at what needs to be done to make PCIe more IoT-friendly. The results showed that it is already quite adaptable for embedded and small devices due to its small footprint and the fact that the required set of features is not an obstacle.
One such rather minor change is a protocol extension that addresses the needs of SoC integration called “enhanced allocation.” This allows designers to create fixed base address registers (BARs) so that they can establish fixed, non-relocatable MMIO resources, thus reducing some degree of complexity. Of course, the need for improved support of small, complex SoCs fits with their increasing use in mobile devices that are also connected to the IoT and mobility also demands increased power efficiency.
Mobile and Low Power Support
The ability to now connect to the MIPI-PHY had already been mentioned and is a big advantage for connecting to mobile devices. In addition, while PCIe’s networking technology is designed to be power-efficient, especially its own PHY specification, using somewhere in the range of a milliwatt, there is definitely room for improvement. The new changes address the goal of reducing link idle power and are getting the idle power down into the microwatt range, supported by what are called L-1 Substates, when both ends are inactive. Device discovery and enumeration also support power management in that they can discover and enumerate devices in the system without requiring new software and drivers.
A new mode for short channel topologies also is available that is called “half swing,” which uses half the launch voltage—400mV—where the normal full swing is 800mV. This is an option that has been available since Gen1. In addition, according to Neshati, the PCIe protocol already contains a robust power management features that can be used to configure the system for dynamic power management.
New Form Factors
By now we are all probably familiar with the card electro-mechanical (CEM) form factor for PCIe devices that plugs into the sockets provided in the normal PC. Of course, the “normal” PC is changing to ever thinner, ever sleeker laptops. Also, the range of intelligent mobile and consumer devices is evolving to ever smaller packages that need to take advantage of the almost universal functionality and acceptance of PCIe.
One new form factor that is targeted at the very sleek, very thin new generation of laptops is the M.2, which is meant to replace the mini-CEM form factor to add features to laptops. According to Neshati, the mini-CEM is not exactly very “height friendly.” M.2 is not just one form factor. It has a flexible I/O technology and multiple socket definitions to support WWAN, SSD and other applications. In addition, there are single-sided and double-sided options to allow trade-offs between high-integration and low-profile options as well as connector or solder-down options. The M.2 form factor is also available in a range of board dimensions with four width options from 12mm to 30mm and seven length options from 16mm to 110mm.
Another emerging form factor—the SFF-8639—is targeted mostly at the more highly integrated new generations of desktops and workstations. The board dimensions are 100.45mm x 69.85mm x 7mm. It is targeted at storage and high-integration applications, especially for the ability to pack large numbers of SSDs onto one board and it supports a data transfer rate of 8 Gtransfers/s in two directions. The connector (Figure 2) both supports PCIe lanes as well as SAS/SATA interface and enables hot plug and hot swap.
Figure 2: The SFF-8639 connector provides PCIe lanes, SAS/SATA and other connections for storage and high-performance devices.
Yet another “between specs” addition that is on the way but not yet released (in Rev 0.9) is an external small cable called OCuLink that can provide outside the box I/O in a variety of high-performance applications (Figure 3). OCuLink has a basic transfer rate of 8Gbit/s with room to scale higher. Thus a four-lane configuration can deliver 32 Gbit/s in both directions. The current version will first be implemented with copper cables but optical is also under development. In fact, OCuLink stands for “optical copper link. “The cable link is targeted at inside the box as well as outside connections, such as displays and external storage. At first glance, OCuLink would appear to fit the same roles as USB 3.0 except that it can hit speeds of almost 7 times what USB is capable of.
Figure 3: OCuLink will provide very high-speed connectivity both within and outside the box starting at 8Gbit/s per lane with optical development potentially offering much higher speeds at a later date.
On the Road to Gen 4
With all these extension both out and in the pipeline there is naturally anticipation of the release of the next PCIe generation, Gen 4. Gen 4 is promising a raw bit rate of 16 Gbit/s, double that of Gen 3, and to be fully backward compatible with previous generations. The promotion talks about its suitability with Big Data applications, which would once more attach it to concepts involving the Internet of Things where small, distributed devices collectively generate huge amounts of data that must be communicated, stored and analyzed at various stages along the way and ultimately in the Cloud.
Currently, the spec is looking at the preliminary release of Rev 0/5 sometime in early 2015 to give developers a preview of what is coming so they can get started with design planning. Then the—tentative and not definitive—expectation is to see Rev 0.7 sometime in the second half of 2015 with Rev 0.9 in the first half of 2016. That, according to Ramin Neshati, should signal that everything is done and call for final comments prior to the final release sometime hopefully still in 2016.
PCI-SIG, Beaverton, OR. (503) 619-0569. www.pcisig.com