As high-performance embedded computing systems continue to achieve new levels of functionality and performance, larger amounts of data must be gathered, processed and analyzed. Applications such as radar data acquisition and video-centric imaging, for situational awareness on the battlefield or high-speed manufacturing lines, have vastly increased the amount of data and the speed at which it must be processed.
For example, next-generation radar data acquisition systems are being built for advanced aircraft such as Northrop Grumman’s E-2D Hawkeye. These will help the U.S. Navy’s Sea Strike offensive capabilities by increasing battlespace awareness, providing theater air missile defense capabilities, improving detection and tracking, and narrowing the link between sensor and shooter for more agile response to time-sensitive targets.
Manufacturers of data acquisition boards and subsystems are leveraging existing hardware off-the-shelf building blocks—such as intelligent I/O controllers, embedded switched fabric interconnect and high-speed fiber interface PMC modules—and adding existing software to keep costs and risk down. Combined with the customization capabilities of onboard FPGA-based IP, these components are producing subsystems that meet aggressive size, weight and power constraints while also delivering high performance.
Meanwhile, real-time video imaging has arrived on the data collecting stage in a big way. Video is playing an increasingly central role in capturing additional data and monitoring operations. On the factory floor as well as on the battlefield, data must be processed and fused in real time and made available simultaneously to all of the system’s nodes. Here, the challenge for design engineers is to maintain the low latency required for real-time data capture and distribution, in addition to the high I/O throughput rates needed to handle large video streams and preserve data accuracy.
Distributed shared memory network architectures based on a ring topology are being utilized to construct high-speed I/O networks that not only meet these needs, but also enable remote processing far from the harsh environments where the gathering of data occurs. Data is captured at multiple stations and sent to several processors, each of which processes different pieces of that data simultaneously.
On another front, a major breakthrough has occurred in the IF data transfer interface. The emerging VITA 49 standard defines a standard way of transferring IF data in a digital, link-agnostic format between analog front-ends and DSP subsystems. Instead of depending on application- and/or equipment-specific interfaces to transmit digitized incoming analog signal data to system elements, the new format defines a data structure for the transmission of digital IF data between multiple sources and destinations for both receive and transmit paths. The standard’s methodology for representing digital IF data can be layered on top of any transport protocol or physical communications link.
The ramifications are clear: OEMs will no longer be tied to vendor-specific interfaces, but can select interoperable system and subsystem components from many vendors based on which ones best fit their applications. As an added bonus, designers no longer must rework system hardware and software each time a source or destination component changes, thus speeding time-to-market.