Boxes Becoming Boards—Technology Transition in VPX

Fractal Realms series. Backdrop of fractal elements, grids and symbols on the subject of education, science and technology

Boxes Becoming Boards—Technology Transition in VPX

As can be seen in the movement toward small form factors (SFFs), card-based standards, like VPX, support new feature sets that enable systems to be greatly reduced in size, weight and power (SWaP), while function and circuit density is increased.

By Ken Grob, Elma Electronic Inc. | February 2016

The Army’s Hardware Convergence effort is a prime example of systems driving boxes to become boards. The strategy considers an increase in function and flexibility, while reducing SWaP and cost by driving toward higher levels of system integration.

Examples of systems packaged at the box level, where implementation can now be done at the board level, include:

  • Servers becoming boards, where an Intel XEON processor-D multicore CPU allows eight—and eventually 16—cores on a 3U VPX board with large DDR4 memory. This will allow a 32-thread system.
  • 10 and 40 Gb high-speed Ethernet switches now implemented on 3U VPX boards: new fabric devices from Broadcom, Marvel and Vitesse enable 3U VPX switches capable of 1000BASE-BX, 10GBASE-KR and 40GBASE-KR Ethernet
  • FPGA system-on-chip (SoC) from Altera and Xilinx allow entire subsystems to be placed on a Eurocard. Examples include SDR, RADAR, and EW applications.

To illustrate these points, a typical system architecture follows, which shows a backplane profile of a converged system.

3.3_figure 1

Figure 1: A backplane profile of a converged system.

Hardware Convergence System Topology

The system design allows payload slots in this backplane to implement functions in one or two slots that were previously built as separate boxes. Reviewing the architecture shown in the diagram above identifies new technology features required of the OpenVPX system topology. Specifically, functional density and operating speed affect the following areas of the system backplane.

  • Backplane interconnect speed: all data paths are high speed
  • Power density per slot: 25 to 45 Watts per slot
  • Transition of I/O from the boards: fiber optic required for high speed Ethernet
  • Clocking schemes: require coax connections for high quality clocks

Additional changes are required in the OpenVPX specification to allow implementation of the new high speed system design.

Clocking and Timing Changes:

  • Radial clocks are introduced and IEEE1588 PTP protocol is applied
  • REF clock moves from 10 MHz to 100 MHz

High-speed Signal Channels Defined by VITA 68:

  • Control Plane and Data Plane requiring 10GBASE-KR rates
  • Fat Pipes comprised of four lanes supporting 40GBASE-KR
  • PCle Gen 3 Interconnect:

  • Operating at 8 GT/sec between slots

    New I/O Connectors for Coax and Fiber Optics:

    • Mixed modes of I/O require fiber optic connections and RF transition via coax.
    • New standards are required to address high speed I/O (i.e. VITA 66.4, VITA 67.1, VITA 67.3)

    Fiber connections use VITA 66.4, and coax connections use VITA 67.1. Fiber transition is done with MPO ferrules, supporting between 12 and 64 fibers. A new standard, VITA 67.3, allows for user-defined contact arrangements in the connector housing.

    3.3_figure 2

    Figure 2: Backplane with VITA 67.3 fiber optic connectors

    Summary

    Technology transition has allowed box level systems to be reduced to 3U VPX boards, making significant gains in SWaP reduction for complex systems. In addressing system designs that use high speed networks and fast local PCIe interconnects, backplane technology has changed. Requirements, such as radial clocks and new I/O connector schemes, have driven changes to the OpenVPX standard, which has evolved to keep up with new system features and data rates. It has proven itself as a standard that can grow with technology change supporting long system lifecycles.