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Doing More by Spreading the Load

Hybrid Devices Maximize Flexibility, Performance and Energy Efficiency for Wearable Technology

The ability to partition tasks among CPU, DSP and programmable logic elements on the same device enables developers to optimize energy, performance and development time.

DR. TIM SAXE, QUICKLOGIC

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Wearable technology plays a pivotal role in the next stage of the Internet of Things by bringing value to individuals through new levels of interconnectedness.  For example, wearable applications today range from high-end sports watches that can help improve an athlete’s performance to glucose monitors that can save lives by alerting patients and doctors.

A key challenge facing software and hardware designers of wearable devices is how to provide advanced processing capabilities, while maintaining a small form factor and minimal power consumption.  Fast time-to-market is important to a product’s success as well, so development time is a key factor, as are development costs and product bill of materials (BOM).

Given that wearable technology is still an emerging market, it is critical that developers also maintain flexibility to be able to quickly adapt to changing market needs and trends.  For example, devices must be able to interface to new types of peripherals, such as motion sensors woven into clothing.  Devices must also be able to support advanced signal processing capabilities to accurately extract data from low-level sensor signals in noisy operating environments.  Furthermore, systems need to be able to implement increasingly sophisticated algorithms; i.e., a sports watch needs to be able to determine whether a person is running, bicycling or weightlifting to accurately assess activity level and calorie count.

Developers have numerous architectural choices for designing wearable devices.  General-purpose CPUs and DSPs provide developers with flexibility through software programmability.  However, they do so with higher energy consumption compared to digital logic.  Similarly, programmable logic provides excellent energy efficiency and performance, but at the cost of increased development cost and time-to-market.

To achieve the performance, energy efficiency and integrated functionality needed to enable next-generation wearable devices, developers need hybrid architectures that blend software programmability with application-specific accelerators and reconfigurable hardware.  Developers can then partition functionality between these different resources so that the most efficient architecture is used for each task based on its complexity and frequency of execution.

Maximizing Energy Efficiency 

Good design is about understanding and balancing tradeoffs for a particular application.  For example, it is possible to get high performance and fast time-to-market, but the design will likely have higher energy consumption and/or a higher price.  Energy efficiency is always an important consideration, typically measured in energy per work unit.  For wearable devices, it often is the highest priority.

Many engineers begin a design by deciding upon the system’s main processor.  They choose an off-the-shelf processor like an ARM or DSP designed to simplify and speed design.  Such processors achieve this through generalization of functionality and software programmability.  

This flexibility comes at the expense of energy efficiency and cost since a general-purpose architecture requires program memory, instruction fetching and other mechanisms to perform what could be implemented more efficiently in a fixed manner directly in logic.  In addition, general-purpose CPUs often have superfluous peripherals or functionality that consume energy unnecessarily.  As a result, the energy constraints of wearable applications often make it unfeasible to utilize off-the-shelf general-purpose processors.  

The calculation for estimating the energy consumed by a system is often simplified to:

energy(total) = power(sleep) x time(sleep) + power(active) x time(active)

To minimize energy(total) , developers design systems to maximize time(sleep) and minimize time(active).  The problem with this simplified approach is that it potentially limits developers to thinking in terms of a single architecture, and that energy is optimized primarily through software design.

For applications that truly need the lowest energy consumption, designers need to rethink how hardware fits into the equation.  Energy efficiency comes from optimization of both software and hardware.  With a hybrid architecture, this is captured in the energy calculation:

energy(total)

Programmable Logic (power(sleep) x time(sleep) + power(active) x time(active)) + DSP (power(sleep) x time(sleep) + power(active) x time(active)) +
CPU (power(sleep) x time(sleep) + power(active) x time(active)

To minimize energy(total), developers need to consider the energy required to perform a task across all of the architectures and determine where to partition it.  For example, reading a sensor using programmable logic requires the system to activate much less circuitry than using a CPU.  A CPU will also take longer to perform this task, further decreasing energy efficiency compared to programmable logic.

Estimating total energy consumption is actually a much more complex calculation.  Developers also need to consider the impact of factors such as time-to-wake when determining the energy efficiency of a task.  For example, raising a CPU from Sleep to Active mode takes a certain amount of time during which the processor consumes energy but does not do any work.  This is, in effect, wasted energy.  Thus, time-to-wake needs to be added to the time it takes to perform a task.  

Energy Efficiency vs Cost and Flexibility

The most energy efficient system would be one entirely comprised of specialized logic.  Such a system could maximize parallelism, while completely eliminating unnecessary logic.  In addition, because processing is performed as quickly as possible, active time would be minimized as well. 

Although energy efficiency is essential, it is not the only consideration.  Table 1 shows the relationship between energy efficiency, cost and time-to-market.  Note that cost can be considered in terms of hardware cost (i.e., silicon die) and development cost (i.e., hardware and software design).  Designing a system completely in specialized logic comes with the tradeoff of more complex design, leading to higher development costs and longer time-to-market.  In truth, the wearable electronics market at this stage is changing too quickly for OEMs to be able to dedicate years to producing an idealized design.  

Table 1
Relationship of design approach to energy consumption, cost, and time-to-market.

A hybrid approach, balancing programmable logic with specialized and general-purpose processor technology, provides the optimal balance of energy efficiency, cost and time-to-market.  The challenge for developers, then, is to determine how to partition their system across architectures to achieve the right balance for their application.

Energy Efficiency vs Complexity

Consider a typical sensor function like calorie counting implemented in a sports watch.  The function involves data processing on several different levels:

1) Read accelerometer sensors – 50 times per second

2) Transform accumulated readings into the frequency domain – once per second

3) Assess the activity (i.e., user is walking, riding a bicycle, sitting) – several times per minute

Breaking down a function using this hierarchy can help simplify partitioning.  Consider that low-level functions tend to be simple and relatively repetitive.  In contrast, high-level functions are more complex and require more decision-making logic.  These high-level functions are also where most of an OEM’s innovation will be implemented.This hierarchy also reflects a function’s relative impact on system energy consumption (Table 2).  Because low-level functions are executed much more frequently than high-level functions, they often represent the highest contribution to active(time) and thus significantly contribute to overall energy consumption.  For these reasons, optimizing low-level functions for energy efficiency in specialized logic provides the greatest return because only essential logic is active.  In addition, low-level functions are often the most simple.  They tend to be fairly linear, with little variation or decision-making involved, making them straightforward to implement in specialized logic.  This maximizes development resources by achieving the most gains in energy efficiency for the least design investment.

Table 2
As the complexity of a task increases, the frequency of its execution, and consequently its impact on energy consumption, drops.

Because high-level functions are executed less frequently, they have less impact on energy consumption.  Consider an assessment function that operates every 5 seconds.  This function represents only a small portion of total energy consumption.  Thus, investing in implementing this code in specialized logic requires a large investment for little gain in energy efficiency.

With a hybrid architecture, high-level functions can be implemented using software on a CPU.  This has a minimal impact on energy efficiency but maximizes the speed with which these functions can be developed.  This, in turn, results in faster development cycles, enabling OEMs to integrate innovation and add value to products quickly and with the greatest flexibility.  Thus, by trading off minimal losses in energy efficiency, substantial gains can be achieved in terms of development time, design flexibility and system cost.

A hybrid architecture supporting DSP functionality provides additional levels of efficiency.  Mid-level functions like signal processing are difficult to implement in specialized logic, and inefficient when implemented using a general-purpose CPU.  With a DSP, these functions can be optimized for energy, cost and time-to-market (Table 1).

Table 1
Relationship of design approach to energy consumption, cost, and time-to-market.

For example, Quicklogic provides programmable devices that implement a complete ARM + DSP + programmable logic platform. Different logic devices offer varying capacities and operating speeds to match an application’s specific requirements (Figure 1).

Figure 1
In a Hybrid Sensor Processing Unit, sensor algorithms programmed in hardware relieve the CPU from executing instructions for the sensing operations.

  One advantage of using a programmable logic platform is that the architectures themselves are flexible.  For example, a general-purpose CPU with a coprocessor is fixed in its implementation.  As the wearable devices market matures, the coprocessor may no longer offer the functionality needed by the system.  With a hybrid architecture, developers have the flexibility to choose a DSP and ARM architecture that matches the requirements of these functions.  As the system evolves over time, the capabilities of these processors can easily evolve as well.

Developers begin their design by considering which functions can be best implemented in hardware (Table 3).  From the remaining functions, appropriate functions are implemented using the DSP.  Then the remaining functions are implemented using the ARM processor.  

Table 3
Implementing a function at the right architectural level provides the best balance between energy efficiency and design complexity.

Quicklogic helps simplify programmable logic design by providing RTL libraries for developers to use.  In addition, the company offers a Flexible Fusion Engine Algorithm Tool (FFEAT) that can accelerate design for engineers who aren’t experts in RTL.  This enables developers to design at a higher abstraction layer, similar to how DSPs can be coded in assembly or C.  While FFEAT does introduce performance inefficiencies compared to native RTL implementations, it can substantially accelerate design.  This enables designers to migrate certain fixed or mature mid- and high-level functions to programmable logic for higher energy efficiency with less of a negative impact on flexibility and development cost.

Today’s general-purpose processors do not provide the energy efficiency required for wearable applications.  Similarly, a solely programmable logic approach does not provide sufficient ease of development or design flexibility.   The wearable devices market can’t afford either of these extremes.  

By taking a hybrid approach, developers can optimally blend the advantages of CPUs, application-specific processors like DSPs, and programmable logic.  Developers can then maximize energy efficiency by optimizing the parts of their system that consume the majority of energy using programmable logic.  The functions that require the least energy, which are typically those where an OEM’s innovation resides, can be implemented using software for the most flexibility and lowest development cost.  In this way, OEMs can achieve optimal performance and energy efficiency.  At the same time, they can simplify development and maintain the design flexibility needed to be able to address new market opportunities at the lowest cost.  

 

 

Quicklogic
Sunnyvale, CA
(408) 990-4000
www.quicklogic.com