TECHNOLOGY IN SYSTEMS
I2C in Small Systems
The Old-Timer in the Background – I2C Bus as a Cost Cutter on Small Form Factors
Surely it is a contradiction to incorporate the latest processor technology alongside a vintage I2C bus on a modern computer module. Congatec disagrees. I2C is a classic, incredibly simple 2-wire bus architecture that has proven its value since the early 1980s.
ROSS WATANABE, CONGATEC
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I²C is capable of assigning up to 1136 addresses configured as master or slave. While it is not the be all and end all in communications, it interfaces proprietary functional units on the baseboard with the computer module at minimal cost. Is it really that simple? Yes. However, a few things need to be considered.
Philips developed the I²C bus in the early 1980s for control tasks in televisions. The Inter-Integrated Circuit (I²C) bus was used to parameterize functional units, program E²PROMs and operate switches. The bus quickly found friends. Chipmakers Siemens (now Infineon), Motorola (now Freescale), NEC, STM and others implemented I²Cs in their semiconductor chips. The first specification was released in 1992 and has been kept up-to-date ever since. The bus became faster and the number of possible functions increased to 1136 thanks to additional 10-bit addressing. The I²C principle works today as it did on day one and is also a cornerstone of the system management bus (SMB), which Intel defined in 1995. The Display Data Channel interface (DDC), developed by the Video Electronics Standards Association (VESA), is effectively also an I²C. Modules from congatec support I²C, SMB and DDC. It is possible to mix I²C and SMB in a design—if you know what to look out for.
The first pitfall lurks in the choice of operating mode. The I²C bus is a master-slave bus with single or multi-mastering. Single-master operation is the simplest method for implementing the I²C bus. But beware: ignoring arbitration and clock stretching can easily lead to communication errors. Processor boards need to provide an on-bus master that transmits up to 400 Kbit/s. All is fine as long as fast slaves do their duty on the baseboard. However, later baseboard versions might be equipped with master functions or include slow slaves. Full design freedom is therefore only guaranteed with the implementation of multi-master operation. Because the I²C bus is electrically built like a wired-AND, it is hot pluggable. Missing or extra nodes on the bus do not affect the logical communication. This saves money during device development because designs can be reduced to assembly variants.
The master always determines the bus clock rate. The specification defines four maximum clock rates: 100 Kbit/s for Standard mode, 400 Kbit/s for Fast mode, 1 Mbit/s for Fast-Plus mode and 3.4 Mbit/s for High-Speed mode. This is where the second pitfall lies in wait. High-Speed mode has lower power and voltage requirements while all other modes are compatible. High-speed segments need to be separated from slower bus parts with switches. To ensure smooth interplay between fast master and slow slave, the slave can slow down the master via clock stretching—provided the implementation supports it. During clock stretching the slave sets the clock rate on low until it is ready for further transmission. Flexible clock rates are a distinct advantage: Slow and fast nodes communicate with each other, and functions can be selected from the entire component range regardless of clock rates. The wide choice also has a positive influence on design costs.
Clock stretching, however, can be a lethal trap if a slave takes a long rest by setting the clock rate continuously on low, thereby effectively paralyzing the bus. To prevent such a blockade, a timeout needs to be defined in the error handling. Speed is not one of the I²C’s strengths because the bus is error prone to fast signals. For this reason, congatec processor modules use the more moderate Fast mode with up to 400 Kbit/s. The I²C shows off its advantages best in elementary tasks. Two simple lines, up to 1136 addresses and hot-pluggability translate into space-saving designs, simple wiring, and a lot of flexibility for little money—an energetic step in cost-cutting measures.
I²C works its magic in the background. It is used in smart cards as well as battery management systems. congatec modules, for instance, support a smart battery manager via the I²C bus. Typical tasks performed by the two-wire bus include setting parameters, identification of hardware components and transmission of status updates. Intelligent I²C switches eliminate the need to use jumpers. As a consequence, the error rate due to incorrect jumper combinations decreases as developers can easily configure via the software interface. The jumperless design is also more vibration resistant. Fewer errors are an active contribution to lowering total cost of ownership. Chances of encountering an I²C are high wherever real-time clocks need setting, memory is waiting for commands, sensors transmit status messages, switches are turned on and off, fans are spinning faster, speakers are getting louder or quieter and brightness and contrast levels of monitors need adjusting. While the bus used may be called a DDC or SMB, it is effectively an I²C.
Know Your Limits
Experience has shown that 30 to 50 cm is a manageable distance for I²Cs without additional drivers. Their use is therefore typically limited to the baseboard and plug-in module. A capacitive bus load of 400 pF is a further limitation. This equals about 20 to 30 nodes on the bus. So what is the use of 1136 addresses if there are only 30 nodes in the segment? There are components with addresses fixed by the manufacturer. Other circuits may have 2 or 3 freely programmable address bits while 4 or 5 bits are set. There are also components that are freely programmable.
This means that there isn’t a connected node behind each available address. It is possible to divide the I²C into segments with extension modules thereby connecting more participants (Table 1). This way the capacitive limits can be overcome while longer distances can be realized with additional drivers. I²C does not have strict baud rates like RS-232. It is a true multi-master bus with collision handling, access arbitration, flexible clock rate and synchronous, bit-serial transmission for simple communication tasks. Despite all of this, the I²C is not a field bus replacement.
How to achieve 1136 addresses with additional 10-bit addressing.
As shown in Table 1, the first address byte contains seven address bits and one bit to distinguish between read and write. This corresponds to 128 addresses. Of these, 16 addresses are reserved, which leaves 112 free addresses. With additional 10-bit addressing, a further 1024 addresses become available. Since both types of addressing are valid simultaneously, the number of possible addresses adds up to 1136 (112 +1024 = 1136).
How to achieve 1136 addresses with additional 10-bit addressing.
How Much of the I²C Is in the SMB?
Both the I²C and the SMB work with clock and data lines, and their basic electrical design and transmission schemes are identical (Figure 1). The logic 1 ground state of both buses is achieved with pull-up resistors. If the line is pulled to ground, this indicates a logical 0. Both buses are connected via a resistor and supplied with reference voltage. This is where the similarities end.
Electric model of I2C bus.
SMB participants can sink a maximum of 350 uA, whereas I²C participants must be able to accommodate up to 3 mA. The bus termination resistors are therefore different, and the influence of the bus capacitance on the signal quality is greater for SMBs. The SMB bus can disable termination altogether during idle mode. Mixed bus systems must take this into account. Otherwise, when the termination voltage is switched back on this could be misinterpreted as start or stop. Also, the clock rate of the SMB is limited to a range between 10 kHz and 100 kHz. I²C, by comparison, works from nearly 0 bit/s to 3.4 Mbit/s in High-Speed mode.
For a general call the I²C master sets address 0 on the bus. This equals a call to all slaves on the I²C bus. SMB works with an optional additional signal, the alert. The slave sends an alert, which the bus master interprets as an interrupt. The bus master responds with a confirmation, whereupon each slave sends its address to the master. The arbitration mechanism selects the slave, which then talks to the master.
SMB recognizes when nodes block the bus. After a timeout of 35 µs all slaves reset their internal state machines and release the bus. I²C does not have a time out. An I²C slave is able to pull the clock line to low for an indefinite length of time. This is used during clock stretching when the I²C slave tells the master that it should wait a little longer before the next transmission. In the worst case scenario, the slave thereby blocks the bus for all.
The Good News
Customers doing hardware design of baseboards benefit because congatec processor boards use the bus for a variety of functions. The feature connector in the starter kit includes the I²C bus signals. Developers can experiment with the bus directly on their test boards. To enable integration into operating systems congatec has developed congatec Operating System Application Program Interface (CGOS). The software interface CGOS provides access to hardware-dependent features yet is independent of the actual hardware.
Figure 2 shows the principle implementation of the CGOS/CGEB interface. The CGEB (congatec embedded BIOS) code is located in the module’s system BIOS. It is 32-bit native x86 object code and executable in any kind of 32-bit protected mode environment. During driver initialization (Figure 2a), the CGEB extension will be copied to the driver’s context and becomes part of the driver (Figure 2b). This mechanism provides independence from the hardware because all low level hardware dependencies are already resolved from the CGEB extension code.
CGOS API, driver initialization (a) and CGOS API, driver up & running (b).
CGOS is the link between BIOS and operating system. It contains a specialized API for I²C functions. I²C bus type selects between SMB, DDC or Primary (true I²C). The CGOS library gives the user hardware-independent bus access. The CGOS API specifies which data is sent; the actual signal handling is the job of the hardware. The interface works on any version of Win32 as well as the following other operating systems:
- Linux (2.4.x and 2.6.x kernel)
- QNX 6.x
- Wind River VxWorks
- On Time RTOS-32
A concrete application example is a smart battery manager that is supported among others by the new COM Express board conga-TCA. I²C provides the user with information on AC or battery operation and battery or charging status. For the operating system to receive this data, the congatec Advanced Configuration and Power Management Interface (ACPI) must be installed at the BIOS level. The operating system itself does not recognize the I²C bus. ACPI is a large table in the BIOS that describes access methods. When the operating system asks for the battery status, the ACPI driver calls the appropriate access method. Whether the information is transmitted via a proprietary network or via the I²C ultimately doesn’t make any difference to the operating system.
The SMBus is used on the new conga-TCA for hardware monitoring and fan control. Conga-TCA is the entry module into the COM Express Type 6 world. On the 95 x 95 mm small board, the workload is shared between an Intel Atom dual-core processor and a STM32F100R8 with ARM 32-bit Cortex-M3 from ST Microelectronics. While the computing power and powerful graphics chipset of the Intel Atom dual core shines in medical, automation, kiosk or digital signage applications, the STM32F100R8 board controller handles power consumption and battery management amongst other tasks. This division of labor also benefits the I²C. The STM32F100R8 with the notoriously energy-efficient ARM core uses I²C even when conga-TCA is in standby mode. The STM32F100R8 has two I²C interfaces. One of them is freely available to the user as I²C; the other is configured as SMB and performs board-specific tasks. SMB is also available for user applications (Figure 3).
The ARM core uses I²C even when conga-TCA is in standby mode
I²C is a modern bus whose basic principle has been incorporated into SMB or DDC. The I²C bus can be operated from within the operating system or application. Around 3000 different functional blocks are available on the market. I²C is the epitome of easy communication at the board level. It remains a contemporary bus despite its age, because it has stayed technically and economically ahead in its field.
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