TECHNOLOGY IN CONTEXT
Power Architecture Stakes its Claim
Power Architecture Combines Rich Features for Embedded
Spanning applications from tiny, dedicated controllers to vast supercomputers, the Power Architecture offers advantages to the embedded space that include parallelism, multicore virtualization, power management and a rich selection of software tools.
FAWZI BEHMANN, POWER.ORG
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Power Architecture processing technology is the common thread for a very broad range of devices, based on 32/64-bit Architecture. It is a ubiquitous architecture with more than a billion Power Architecture-based chips that have been built into electronics equipment since 1991.
Power Architecture technology is the basis for an extraordinary range of products, from supercomputers with 213,000 processors to tiny automotive controllers dissipating less than a watt of power. Power Architecture technology is used in everyday household electronics—printers, HDTVs, video recorders, game consoles—as well as more exotic electronics, such as satellites and the Mars Rover Lander. This makes it well suited for any advanced electronic application offering the best performance per watt.
Rich Set of Chip Families, Diversity, Applications and Market Share
Power Architecture technology underlines many well-known chip families for 32-bit and 64-bit architecture, including the Cell Broadband Engine for game consoles, Px series for microcontrollers, PowerQUICC, QorIQ P & T series for networking and communications. The list continues with Packet Pro for WLAN and Storage, Axxia series for carrier grade and core networks, 7xx & 9xx for mission-critical applications and High Performance Computing (HPC), POWERx for servers & workload optimization, Blue Gene supercomputers and Watson, licensable cores, full featured Virtex FPGAs from Xilinx and hybrid processing devices (Figure 1).
Power R&D roadmap delivering scale, scope and range.
Every Power Architecture technology-based chip is rooted in the Power Instruction Set Architecture (ISA) and processing specifications spanning server and embedded computing capabilities. Power ISA is the only architecture in the market that has proven implementations from the smallest devices to the largest supercomputers while covering a diverse set of markets. Power ISA features are familiar to thousands of software, hardware and tool developers who have worked with PowerPC devices for many years. The most recent Power ISA 2.06 extends the edge Power ISA has in HPC and computation-intensive workloads; provides enhancements to the server space such as memory management, processor version compatibility features and cache management; and also introduces a number of capabilities for the embedded space such as embedded hypervisor, energy management, multicore and multithreading.
According to IMS Research, Power Architecture is $4.4 billion of the total 32/64-bit microprocessor market spanning the eight major markets and expanding into 30 vertical market segments. Among ARM, MIPS, SPARC, X86 and others, Power Architecture microprocessor revenue was ranked as the number one worldwide market share leader in 32-bit MPU, and the number two worldwide market share leader in 64-bit CPU (Figure 2).
Power Architecture is ..8 billion of total 32/64-bit microprocessor market spanning eight major (embedded and compute) markets.
Power Architecture—Power ISA Key Differentiation
Scalability, reliability, flexibility and the open collaborative model of Power.org are some of the characteristics that differentiate the Power ISA from all others and influence the evolution of Power Architecture into a unique position.
“Set-tops to Teraflops” is the tagline that Power.org uses to communicate the inherent scalability of the Power Architecture to the industry. Power Architecture covers the most diverse set of markets including consumer electronics, industrial control, telecommunications and networking, high-performance computing, IT and commercial systems, aerospace and defense, high-end printers and imaging solutions. This is a testament to Power Architecture’s scalability in that it can address a vast array of applications while preserving the binary compatibility of software.
The reliability of Power Architecture implementations is evidenced by the many mission-critical applications in aerospace and defense, such as all the Mars Rover landings that used Power Architecture chips. Power Architecture maintains the leading share of safety-critical automotive embedded systems and has a proven track record of reliability in servers with the lowest soft error rates under a barrage of proton and neutron radiation.
Power ISA covers both 32-bit and 64-bit variants and provides facilities for expressing instruction level parallelism (ILP), data level parallelism, and thread level parallelism that give the programmer the flexibility to extract the particular combination of parallelism that is optimal. The ability of Power Architecture to provide instruction, data and thread level parallelism has enabled a variety of parallel systems, including some notable supercomputers. Power ISA allows exposing and extraction of ILP primarily because of the RISC principles embodied in the ISA. The reduced set of fixed length instructions enables simple hardware implementation that can be efficiently pipelined, thus increasing concurrency. The larger register set provides several optimization opportunities for the compiler as well as the hardware.
Processors implementing the Power ISA have been used to create several notable parallel computing systems, including the IBM RS/6000 SP, the Blue Gene family of computers, the Deep Blue chess playing machine, the PERCS system, the Sony PlayStation 3 game console and the Watson system that competed in the popular television show Jeopardy!
Multicore SoC and Virtualization
Power Architecture technology was an early participant in the world of multicore SoC. IBM Systems and Technology Group and Power Architecture embedded partners and customers have been implementing multicore designs since 2001. The ubiquitous PowerQUICC processors from Freescale, which were launched in the mid ’90s, have always been heterogeneous multicore devices. In 1995, Freescale introduced MPC860, which had two cores—one based on Power Architecture technology and the other was proprietary RISC architecture. In 2001, IBM’s POWER4 incorporated dual cores on a single die. It also was the first to implement a multi-chip module containing four POWER4 microprocessors in a single package. More recently, Freescale’s QorIQ families (P1, P2, P3, P4 and P5) implement from 1 to 8 Power Architecture cores, emphasizing hypervisor and virtualization. Additionally, the POWER7-based supercomputer, Blue Waters, was announced to support 200,000 processors, bringing multi-petaflops performance in 2010-2011.
The challenge of how to efficiently program and automate software development for multicore devices has been addressed by Power.org via multiple ISA and technical initiatives. Power ISA 2.04 was finalized in June 2007 and includes changes regarding virtualization, hypervisor functionality, logical partitioning and virtual page handling. Additional enhancements resulted in ISA 2.05 released in December 2007, which supports decimal arithmetic and server hypervisor improvements. Power ISA 2.06 was released in February 2009 and included extensions for the POWER7 processor and e500 multicore regarding hypervisor and virtualization on single and multicore implementations for the embedded market. Thus, Power ISA 2.06 enabled virtualization for embedded hypervisor and other virtualization technologies.
In the embedded space, the hypervisor is a true hardware-supported operating mode that ensures protection of the virtual kernel from guest operating systems. Thus, the hypervisor allows different software systems to run on different cores at the same time with high integrity. This approach allows each software system and its associated private hardware resources to be protected. While different systems are insulated from direct interactions, software systems can establish communication mechanisms with other software systems in a controlled and reliable manner. This results in simplifying software development by creating an abstraction layer of capabilities for the underlying cores.
Power Architecture cores provide important capabilities for dynamic power management. Some of these are enabled internally in the core. For example, it is common for execution units in the processor pipeline to be power-gated when idle. Furthermore, Power Architecture cores offer software-selectable power-saving modes. These power-saving modes reduce function in other areas, with some modes limiting cache and bus-snooping operations, and some modes turning off all functional units except for interrupts. These techniques are an effective way to reduce power, because they reduce switching on the chip and give operating systems a means to exercise dynamic power management.
But sometimes only the application software running on the processor has the knowledge required to decide when power can be managed without affecting performance. Recognizing this fact, Power Architecture Embedded Supervisor Architecture provides application software with a means for power-optimized solutions through the wait instruction (Power ISA 2.06). This instruction allows software to initiate power savings when it is known that there is no work to do until the next interrupt. With this instruction, power savings can now be achieved through user-mode code. This feature, for example, is well matched to the requirements of the LTE market segment, which requires that total SoC power be managed effectively. The combination of CPU power-savings modes, the wait instruction and the ability to wake on an interrupt has been demonstrated to achieve deep sleep power savings with wake up on external event—with no packet loss.
Software Development Environment
Power Architecture technology has the largest breadth and depth of development tools support in the industry. As expected, tools naturally congregate around the market segments where Power Architecture technology is popular: servers, storage, networking, communications, automotive and digital media. Power Architecture technology is supported by virtually all major operating system platforms and most minor ones as well.
Full system simulation provides virtualization capabilities for the Power Architecture community and helps software developers debug at the system level instead of at the individual board level. Developers are able to run simulations of their full systems, sometimes containing hundreds of different boards with many different kinds of processors, SoCs, devices and communication buses. This simulation helps identify performance enhancements and improves time-to-market through early identification of system trouble spots.
Power.org and its members further advanced Power Architecture technology, completing a number of vital initiatives including Power ISA standards, hypervisor, virtualization and energy management, enabling the highest performing processors and cores for the server and embedded space.
Advancements in the Power Architecture technology continue to provide designers and developers with scalability, reliability and flexibility needed in their diverse markets. Moving forward, Power Architecture technology’s focus on energy management, multicore/virtualization, SoC platforms and software development environments will enable Power Architecture technology to continue to be a ubiquitous architecture in the industry, helping to drive many new and exciting applications.