PRODUCTS & TECHNOLOGY
PLX Technology Expands PCI Express Gen3 Switch Family
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Three new high-performance, feature-packed devices compliant with the PCI Express Gen3 r1.0 Specification are aimed at enabling new, more powerful designs in servers, storage and communications platforms. The new ExpressLane PEX8749 (48-lanes, 18 ports), PEX8733 (32 lanes, 18-ports) and PEX8725 (24 lanes, 10 ports) PCIe Gen3 switches from PLX Technology blend innovation and high port counts. With the debut of these three new switches, PLX is expanding its PCIe Gen3 portfolio to 11 highly flexible devices ranging from 12 to 48 lanes, and three to 18 ports.
Integrated into each new PLX PCIe Gen3 multi-root switch device are performancePAK features, including two non-transparency (NT) ports, four direct memory access (DMA) engines, two virtual channels (VCs), and up to 12 ports for spread spectrum clock (SSC) isolation. The NT feature enables host failover and redundancy and has been widely used by tier-one OEMs since it was developed in early PCI technology. The on-chip DMA engines enable designers to increase the performance of systems by moving data among endpoints or between memory and endpoints without sacrificing CPU bandwidth. Support for two VCs enable users to prioritize traffic to support desired quality of service (QoS). The SSC clock isolation for each x4 port of the device allows designers to create large systems with each subsystem running its own SSC clock.
In addition to x16 and x8 ports, these switches offer native x2 and x4 ports that enable development of large arrays of SSD-based systems with fewer switches. Also included is the support for PCIe specification engineering change notices (ECNs) such as multicast, access control service (ACS), alternative routing-ID interpretation (ARI), atomic operations, and optimized buffer flush/fill (OBFF). PLX PCIe Gen3 devices are fully backward compatible with Gen2/Gen1 devices and recommended for all new designs. The PLX Gen3 devices can be used to create Gen3 slots using their bridging capability in a Gen2 platform.
The new switches are supported by PLX’s visionPAK system debug tools, such as Performance Monitoring, Error Injection, Packet Generator, and the ability to measure both width and height of a SerDes eye using PLX’s free software development kit (SDK). The on-chip hardware debug features, complemented by the SDK software, offer instant logic analyzer support, high-speed scope view, pattern generation and error injection—capabilities that shed the cost of spending hundreds of thousands of dollars on test equipment. Volume pricing is $35.00 to $70.00.
PLX Technology, Sunnyvale, CA. (408) 774-9060. [www.plxtech.com].