CPU Meets I/O in System Management

Customizing a Microcontroller for Hardware Platform Management

I/O customization can substantially benefit the functionality and cost-effectiveness of a hardware platform management controller, especially one that takes advantage of the flexibility inherent in an intelligent mixed signal FPGA.


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When the subsystem CPU is a microcontroller and its job includes hardware platform management for a larger board or module, it is highly desirable for the controller to integrate management-friendly I/O facilities. One way to accomplish such integration is by using an intelligent mixed signal FPGA, such as Microsemi’s SmartFusion, which combines a microcontroller, a programmable analog subsystem and a field programmable logic array. The latter two subsystems allow the traditional I/O facilities of the microcontroller to be augmented for this application, effectively moving the line between CPU and I/O to integrate application-specific I/O with the CPU.


The examples given here focus on hardware platform management in boards and modules targeting the PICMG xTCA (AdvancedTCA, AdvancedMC or MicroTCA) family of architectures, but the same ideas are applicable to other standardized and proprietary management architectures. The article titled, “Using Intelligent Mixed Signal FPGAs for Hardware Platform Management,” in the October 2010 issue of RTC, introduces this overall concept, shows its applicability to other platform architectures beyond xTCA, and describes an example management controller based on this approach and an intelligent mixed signal FPGA, the SmartFusion device.  

Customized I/O Benefits an xTCA Carrier IPM Controller

An xTCA Carrier IPM Controller (Carrier IPMC) handles hardware platform management for an AdvancedTCA (ATCA) board that implements slots for hot-swappable AdvancedMC (AMC) mezzanine modules.  

A Carrier IPMC interfaces up to an ATCA Shelf Manager via a dual redundant I2C-based IPMB-0 and down via a set of local intelligent platform management buses (IPMBs) called IPMB-Ls to the management controllers on its AMC mezzanine modules. In xTCA, a Carrier IPMC can need up to nine IPMB-Ls; that plus IPMB-0 yields a total of up to eleven I2C ports, almost double the largest number of such ports we know of on a standard microcontroller, even one that is optimized for management applications. With a carrier IPMC based on an intelligent mixed signal FPGA, extra I2C ports can be added in the FPGA fabric, as needed.

xTCA allows IPMB-L to be implemented on a multi-drop basis, where a single IPMB is shared across all the modules. However, that approach has at least two downsides. The first is that each of the IPMB-L legs must be isolated from the others, so that, for instance, an AMC that is being hot swapped in or out of the AMC carrier board doesn’t corrupt that shared bus. The isolation devices increase the size and cost of the carrier IPMC. Second and more importantly, a single misbehaving IPMB-L node can disrupt traffic for all the other nodes, affecting reliability, and only one of the nodes can be sending a message on the bus at any given time, affecting performance. Both of these limitations are removed when each IPMB-L is logically separate.

Figure 1 shows a full-function carrier IPMC application based on SmartFusion, including what are likely to be one or more payload CPUs (say, PowerPCs or Xeons) on the ATCA board and a fabric switch—assumed to be Ethernet in this case. In addition to the IPMB-L support, FPGA fabric-based I/O enhancements include a Low Pin Count (LPC) PCI bus subset link between the payload CPU(s) and the IPMC and additional UARTs for serial consoles. It additionally provides power rail control, which also leverages the microcontroller and the programmable analog subsystem.

Figure 1
Extensive I/O requirements of an xTCA carrier IPM controller.

There is one final I/O extension to mention for the Carrier IPMC in Figure 1. The Ethernet interface in the SmartFusion device implements the Reduced Media Independent Interface (RMII). This is perfect for compliance with the Network Controller Sideband Interface (NC-SI), an open standard for connecting management controllers to NCs. See “LAN-attached TCA Management Controllers: How to Build and Use Them,” in the August 2009 issue of RTC and check for a copy of the NC-SI specification.

Figure 1
Extensive I/O requirements of an xTCA carrier IPM controller.

In the above context, however, the management controller needs to connect into a switch and often RMII is not an option there. Fortunately, the RMII connection can be routed through the FPGA fabric and converted to some other Media Independent Interface (MII) variant that is switch-compatible.

I/O Customization for MicroTCA Management Infrastructures

MicroTCA (µTCA) is a smaller, lower-cost complement to ATCA that also includes a full-featured hardware platform management architecture as elaborated in “MicroTCA.0 Specification Adapts and Extends PICMG Hardware Platform Management Facilities” in RTC, November 2006).

Figure 2 shows the key infrastructure portion of a potential MicroTCA carrier, which is designed to support up to twelve AdvancedMC (AMC) modules. Only four are shown in the figure; these are the same AMCs that can also be installed in ATCA carrier boards and managed by a Carrier IPMC. The infrastructure elements include several levels of hardware platform management, plus a central CPU and an Ethernet switch fabric for the carrier.

Figure 2
Key infrastructure elements of a MicroTCA carrier.

One way to realize the infrastructure of a MicroTCA carrier is with distinct functional modules. The main infrastructure elements in Figure 2 would be implemented on a MicroTCA carrier hub (MCH) module, possibly with two of them for redundancy. The power supply for the carrier would be implemented in up to four MicroTCA-specified power modules, which may support redundancy as well. Carrier cooling could be handled by up to two MicroTCA-specified cooling units.

Figure 2
Key infrastructure elements of a MicroTCA carrier.

Figure 3a shows how a passive backplane could provide module slots for the above infrastructure functions and four AMCs. Below each slot are communication link stubs representing the various types of infrastructure links implemented in the carrier. This modular infrastructure approach is the most flexible and has the most architectural headroom, but it isn’t necessarily cost-optimized. It takes advantage of roughly the same FPGA-based I/O customization as for the Carrier IPMC, but more of it—up to 13 IPMB-L legs, for instance!

Figure 3
Modular (a) and integrated (b) MicroTCA infrastructure approaches.

Alternatively, the infrastructure of a MicroTCA carrier can be integrated as shown in Figure 3b. An active backplane or motherboard can directly implement the main infrastructure elements as well as the supplementary infrastructure elements, leaving just the AMC modules to be installed in distinct backplane slots.

Figure 3
Modular (a) and integrated (b) MicroTCA infrastructure approaches.

An integrated infrastructure likely offers the best opportunities to optimize a MicroTCA carrier for cost and/or size. This architecture also provides even more opportunities for I/O customization. Substantial new functional blocks can be added to an intelligent mixed signal FPGA-based MCMC to implement fan control, perhaps via an IP block that combines PWM and tachometer functions. In addition they can provide enhanced power management capabilities, including monitoring all the AMC power channels.

I/O Customization Integrates Power Rail Management 

Power rail sequencing during power-up or power-down of an xTCA board or module is another critical supervision function in xTCA platforms. It requires care and in-depth understanding of all the requirements associated with individual chips on the board as well as with the overall system reliability and safety considerations. The complexity of the task increases when the number of analog and digital supplies and/or the number of analog or digital point of load (POL) regulators increases, and can be further complicated by system safety requirements. 

To illustrate with a simple example, consider a scheme where a power rail is not enabled until several other power rails, in a defined sequence, are turned on and reach a minimum threshold voltage. And if a power rail falls below a minimum voltage, a safe shutdown of the already enabled POL regulators must occur. In actual boards or modules, the fault detection and response requirements can be much more complicated, highlighting the need for complete understanding of all the system requirements. 

Moreover, analog and digital power supplies may require real-time monitoring, trimming and current limiting, adding to the required sophistication of the power management subsystem. Additionally, when down time is not allowed, power management architects usually implement redundancy schemes to minimize the impact of unavailability of one of the power management units. 

All the above constraints get translated for the development and integration teams into a high demand for digital and analog

I/Os, data acquisition resources, data transfer schemes and processing power. 

Fairly complex power management schemes can be integrated into an ATCA IPMC that is based on an intelligent mixed signal FPGA such as the SmartFusion device, as shown in Figure 4. ARM Cortex-M3 firmware can supervise the overall subsystem, using the results of data samples retrieved and assessed (e.g. threshold tested) by the programmable analog function. The Analog Compute Engine (ACE) sets flags that are directly available to FPGA logic. These flags can represent, for instance, over- or under-threshold conditions, as inputs to fault detection logic implemented in the FPGA fabric. That logic can control the actual power enables, over-riding, if necessary, the normal sequence of enables or disables determined by the firmware supervisor. The FPGA fabric can also include a Pulse Width Modulator (PWM) function that, under Cortex-M3 control, provides margining controls to the trim inputs of the power supplies.

Figure 4
Power supply management integration in SmartFusion-based ATCA IPMC reference design.

Extending the I/O interfaces of a microcontroller in the innovative and flexible ways sketched in the example above may allow board and module architects to forgo the use of dedicated power management chips, because the responsibilities of those chips are integrated into the hardware platform management controller. This can result in footprint and bill of materials savings and may enable more sophisticated power management paradigms to be implemented. Furthermore, all the key resources that participate in the power management implementation—the Cortex-M3, analog subsystem and FPGA fabric—are programmable, so it is possible to test different approaches and select the best one based on experiments with the physical board or module.  

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