RTC Magazine

PCI-SIG Releases PCI Express 3.0 Specification

PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) industry standard input/output (I/O) technology, has announced the availability of the PCIe Base 3.0 specification to its members. The PCIe 3.0 architecture is a low-cost, high-performance I/O technology that includes a new 128b/130b encoding scheme and a data rate of 8 gigatransfers per second (GT/s), doubling the interconnect bandwidth over the PCIe 2.0 specification. PCIe 3.0 technology also maintains backward compatibility with previous PCIe architectures and provides the optimum design point for high-volume platform I/O implementations across a wide range of topologies. Possible topologies include servers, workstations, desktop and mobile personal computers, embedded systems, peripheral devices and more. 

The PCIe 3.0 specification extends the data rate to 8 GT/s in a manner compatible with the existing PCIe 1.x and 2.x specifications and products that support 2.5 and 5 GT/s signaling. This bit rate represents the most optimum tradeoff between manufacturability, cost, power, complexity and compatibility. Based on this data rate expansion, it is possible for products designed to the PCIe 3.0 architecture to achieve bandwidth near 1 gigabyte per second (Gbyte/s) in one direction on a single-lane (x1) configuration and scale to an aggregate approaching 32 Gbyte/s on a sixteen-lane (x16) configuration. The new 128b/130b encoding scheme also allows near 100% efficiency, offering a 25% efficiency increase for 8 GT/s as compared to the 8b/10b efficiency of previous versions, which enables the doubled bandwidth.

This evolutionary specification integrates a number of enhancements to the protocol and software layers of the architecture. These enhancements range in scope from data reuse hints, atomic operations, dynamic power adjustment mechanisms, latency tolerance reporting, loose transaction ordering, I/O page faults, BAR resizing and many more extensions in support of platform energy efficiency, software model flexibility and architectural scalability.

VPX REDI Standard Reaches ANSI/VITA Ratification

The VME Bus Industry Trade Association (VITA) has announced the ratification by ANSI and VITA of the VPX REDI base specification and several dot specifications. VPX REDI is a computing standard defining mechanical specifications for cooling and maintenance strategies for VPX systems. VPX is an embedded computing platform utilizing the latest in a variety of switch fabric technologies in 3U and 6U Eurocard format modules. 

VPX REDI was inspired by the need for higher density electronics, increased power draw that requires more effective cooling strategies, and rugged and maintainable modules. VPX REDI targets the requirements of Commercial-off-the-Shelf (COTS) platforms for defense and aerospace, defining mechanical design implementations for embedded computing modules with three primary design objectives: Accommodating cooling methods including forced air, conduction and liquid cooling; adding features compatible with ESD covers required for two-level maintenance strategies; and facilitating module designs with components on the secondary side of the circuit board.

The following VPX REDI specifications have been ANSI/VITA ratified. 

• ANSI/VITA 48.0-2010: Ruggedized Enhanced Design Implementation Mechanical Base Specification, which defines a mechanical implementation for plug-in units.
• ANSI/VITA 48.1-2010: Mechanical Specification for Microcomputers Using Air Cooling Applied to VPX
• ANSI/VITA 48.2-2010: Mechanical Specification for Microcomputers Using Conduction Cooling Applied to VPX
• ANSI/VITA 48.5-2010: Mechanical Specification Using Air Flow-through Cooling Applied to VPX

Emerson and Mercury Team to Promote Interoperability in Mil/Aero

Emerson Network Power and Mercury Computer Systems have announced today that they will collaborate to promote interoperability on open standards-based subsystems for military and aerospace applications. This alliance seeks to provide interoperability between the companies’ rich range of embedded computing solutions, in order to enable defense customers to migrate their performance away from proprietary closed architectures to flexible open solutions, reducing risk and lowering development and deployment costs as a result.

This alliance combines the strengths of both companies—Mercury’s leadership in high-performance signal and image processing, open standards hardware and software and systems integration and services—with Emerson Network Power’s leadership in standards-based embedded computing technology for the telecommunications, industrial automation, aerospace/defense and medical markets.

VIA Labs Scores USB-IF Certification for USB 3.0 NAND Flash Controller

VIA Labs has announced that the VIA Labs VL750 USB 3.0 to NAND Flash Controller has been certified by the USB Implementers Forum (USB-IF) for SuperSpeed operation, ensuring high quality multimedia and more immersive and compelling applications. The comprehensive suite of tests conducted as part of the USB-IF Compliance and Certification Program ensures that certified devices are interoperable and backward compatible with existing USB devices, while also offering the speed and power enhancements of the new USB 3.0 specification.

Moreover, the VIA Labs VL750 packs this SuperSpeed punch within a single chip controller, eliminating the need for a second bridge chip and enabling more compact, more power-efficient and more cost-effective Flash drives. As a USB-IF-certified product, the VIA Labs VL750 will be added to an Integrators List of compliant SuperSpeed USB devices, which is available to manufacturers at www.usb.org/developers/compliance. This List enables manufacturers to quickly find USB 3.0 components that have met the USB-IF Certification and Compliance Program criteria. 

The VL750 is a highly integrated, single chip USB 3.0 to NAND Flash solution. Featuring a 4-channel memory controller with interleaving support, blisteringly fast data transfer speeds of 100 Mbyte/s or more can be achieved. In USB 2.0 mode, the VIA Labs VL750 offers class-leading performance with transfer speeds of up to 35 Mbyte/s.

Report Shows Modular Form Factors Build Good Growth

A new report from IMS Research, analyzing the world market for embedded computer boards and modules, expects modular form factors, such as COM Express, to grow strongly over the next few years. World COM Express revenue growth is forecast at over 20% year-on-year, with annual revenues reaching over $270 million in 2014; unit shipments of over 790,000 are projected.  

The COM Express standard offers the advantages that application development, and therefore time-to-market, is quicker than with most other standards; board customization is easy and inexpensive (even for low volumes); and product lifecycle costs are lower. The modular format of the COM Express standard and its compatibility with emerging ultra-small form factors, such as nanoETXexpress, will continue to drive adoption.

Form factors that have a modular approach give OEMs and end users the advantage of interchangeability. This flexibility allows companies to cherry-pick the boards and modules that best match the application. Also, if a certain part of the system needs updating or replacing, then only that part is affected; which gives a cost and time advantage over non-modular solutions, as the rest of the system remains unchanged.

The modular approach to embedded computer boards and modules will become increasingly important in the near future as advantages of cost, time-to-market and system flexibility pull end users away from adopting other board types. 

New Virtex-7 HT Devices Enable 100 - 400 Gbit/s Apps and Beyond

A new family of Virtex-7 HT FPGAs from Xilinx has produced 28 Gbit/s serial transceiver performance required for next-generation 100 - 400 Gbit/s applications. The 28nm FPGAs are intended to enable communication equipment vendors to develop the integrated, high-bandwidth-efficient systems necessary to keep pace with the exploding global demand for more bandwidth in the wired infrastructure and datacenters. The new devices are equipped with the industry’s highest-speed and lowest jitter serial transceivers available in an FPGA to support stringent optical and backplane protocols, according to the company.

Built with four to sixteen 28 Gbit/s transceivers complying with OIF CEI-28G, the Optical Internetworking Forum’s Common Electrical I/O specification for 28 Gbit/s, Virtex-7 HT devices are designed to interface to next-generation CFP2 and QSFP2 optical modules that will be used in next-generation 100 - 400 Gbit/s system line cards. The devices also have up to seventy-two 13.1 Gbyte/s transceivers and can offer up to 2.8 Tbyte/s full duplex throughput. This extends the Virtex family’s total system performance, with 2x the logic capacity, 1.3 greater memory bandwidth, 2x better static power efficiency, and now 2.7x higher bandwidth over comparable competing devices.

The devices’ feature mix allows for a wide range of applications, from low-cost 100G “smart gearbox” chips with 290,000 logic cells to the world’s first 400 Gbit/s FPGA with 870,000 logic cells including applications from 100 Gbit/s, 2 x 100 Gbit/s or 400 Gbit/s interfaces, and efficient connectivity to legacy system side interfaces based on 3 Gbit/s or 6 Gbit/s as well as 10 Gbit/s ASICs and ASSPs. This means Virtex-7 HT FPGAs can be used in applications such as 100 Gbit/s line cards supporting Optical Transfer Unit-4 (OTU-4) transponders, muxponders or service aggregation router SAR (), lower cost 120 Gbits packet processing line cards for high demanding data processing, multiple 100G Ethernet ports bridges, 400 Gbit/s Ethernet line cards, base stations and remote radio heads with 19.6 Gbit/s Common Public Radio Interface (CPRI) requirements, and 100 Gbit/s and 400 Gbit/s test equipment.

CANopen SIG Service Robots Established

CAN in Automation (CiA) has established the CANopen SIG (Special Interest Group) for service robots. Several Japanese research institutes and companies participated in the inaugural meeting, which took place in Tokyo. It was agreed to standardize the mapping of the Robot Technology Component (RTC) specification to CANopen network technology. This would allow service robot manufacturers to make easy use of off-the-shelf CANopen devices such as motion controllers and sensors. The robot application software will call RTC functions (middleware) while the CANopen details are hidden to the software engineer. This will simplify software development and would allow reuse of already existing RTC programs. The RTC specification has been developed by the nonprofit OMG (Object Management Group).

The scope of the SIG also includes the development and maintenance of recommended practices for existing CANopen profiles to be used in service robot applications (e.g. CiA 402 motion controllers, CiA 404 sensors, CiA 406 encoders, CiA 418/9 batteries and chargers). If necessary, the SIG will develop and maintain dedicated CANopen profiles for service robot subsystems such as grippers or multi-axes controllers.