New Challenges Face Even Smaller Boards


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One of the primary driving forces behind the SFF revolution has been Moore’s Law. For those few of you who may not be acquainted with this little jewel, it states that transistor densities double roughly every 18 months. That means that next year’s chips will pack twice the number of transistors into the same die space. Processors we were using only ten years ago would take 2% of the same die today. And it means that next year’s processors will need to integrate big chunks of functionality to fill the available space.  

Why not just make the die smaller? With today’s 1000-plus ball microBGA packages, most of these designs are pin-limited. That means the space required for the I/O pin pads defines the size of the die, not the number of transistors required for the basic functionality. Hence, all those extra transistors are free—sort of.

Over the last decade, the trend has been to fill this extra space with no-brainers—first with lots of cache and next by adding processor cores. Simple to design and very low market risk. But in addition, we’ve seen functionality that was originally supplied through additional components sucked into the processor or, more often, the chipset. We’ve become used to chipsets with Ethernet MACs, lots of USB ports, SATA and graphics controllers. Remember that Moore’s Law applies to chipsets as well as processors.  

Finally, in just the last year or so, we’re seeing the chipset logic itself get sucked onto the processor die. The great advance of the new Tunnel Creek parts is because the transistors that implement what used to be called the northbridge or memory hub, consisting primarily of a memory controller and a graphics controller, got sucked into the processor chip itself, saving board space big time.

This evolution has translated directly into smaller and smaller CPU boards. SBCs have moved from the decidedly unsmall EBX form factor of the late 80s (203 x 146 mm) to today’s smallest expandable SBC standard, Pico-ITXe, at 100 x 72 mm without any loss of functionality. And the evolution of Computer-on-Module (COM) technology takes the size down even smaller, with today’s smallest COM, CoreExpress at 58 x 65 mm. All these advances in size are completely due to Moore’s Law.

But there is a threat on the horizon. Actually, it is already here—one that we have been dealing with for some time. Just as chips are pad-limited, the challenge in these very small boards has been how to get all the I/O off the board. Standard PC-style connectors such as Ethernet, USB, audio, video and/or graphics displays and power take far too much space for even the larger of the small form factor boards. Some years ago, the smaller boards, such as PC/104 began using pin headers for virtually all I/O, using transition cables to convert from a pin header to a PC-style connector. While this solution frequently created a cable rats nest in embedded systems (and the resulting manufacturing / maintenance nightmare), it worked. But with sizes shrinking even further, the .1 inch, or even the 2 mm pin headers are simply too large to support the amount of I/O on some of these small boards. Something new is needed.

But, you might say, COMs don’t have that problem. COMs pass all the I/O through one or more higher density connectors to the baseboard.  But in essence, they simply “pass the buck” from the CPU board to the baseboard. Even if COMs were to shrink another 50%—not an impossibility if you follow Moore’s Law through the next 3-5 years—getting the I/O off the baseboard will limit overall size reductions. What good is a tiny COM with a super dense processor chip on an EBX-sized baseboard? And in this case, dumping more functionality on the baseboard is far from free and may have little or no use in the end application.

It’s time for a “from scratch” creative solution that will allow SFF processor boards to continue to shrink as processor densities grow. Intel’s Light Peak optical initiative is promising, but lots of questions remain—particularly, how can it be applied to embedded applications where I/O feature content varies from board to board? Our problem is size, not speed. How will this help?  

Whatever the solution, it must be pervasive and ubiquitous—and supported by connector and board manufacturers everywhere. Let’s get going.