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EDITORIAL

System on Chip (or Two) Coming to a Design Near You?

TOM WILLIAMS, EDITOR-IN-CHIEF

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Are developments in silicon going to play havoc with this explosion of small form factor modules that has been recently sprouting like mushrooms in a moist cellar? With this issue,  RTC is including a poster designed to help sort out this variety, but that is sure to get your esteemed editor a flurry of phone calls and emails demanding to know why such and such was not included and why this or that was. I won’t repeat the rationale here because it is in the text of the poster and we stand behind it.

However, the burgeoning variety of small modules—be they standards, the work of ad hoc consortia or completely proprietary designs—is indicative of an ongoing struggle to optimize the balance between the more widely applicable CPU/memory section of a design and the more specialized, application-specific portion, which is the I/O. The reasons are fairly clear. Microprocessors and semiconductors are made by very large companies and designed to be as widely applicable as possible within their target markets. I/O on the other hand tries to be as focused as possible on the precise needs of the application. This has led to what might be described as the “partition problem.”

Among the more recent answers to the partition problem are computer-on-module (COM) form factors such as COM Express, Qseven, CoreExpress and others. Stackable CPU boards, such as PC/104, EPIC and EBX, have long addressed this problem. The trouble is that this solution inevitably leads to at least a two-board system . . . at least. In the past, the only way to get to a single-board, or ideally a no-board solution, was to go with a full-custom ASIC, FPGA or SoC. The vast majority of embedded designs does not have anywhere near the volume to justify the up-front expense.

A number of semiconductor manufacturers will do a custom CPU design for a high-volume customer and then, having designed it and recovered their own costs, add that mix of core and peripherals to their catalogs. Then it is up to the designer to page through these tomes hoping to find the closest match to his or her needs. Happy hunting! 

Now, however, developments in silicon may be taking us in a different direction. These developments may appear different on the surface, but they are all attempts to address the partition problem in silicon rather than on separate modules. What we have tried to describe as application services platforms (ASPs) have made their first appearances in the form of the SmartFusion devices from Actel and the Extensible Processing Platform from Xilinx. These were preceded by the Programmable System on Chip (PSoC) from Cypress Semiconductor. The three have in common the inclusion of a microprocessor (all ARM designs) with its normal complement of peripherals along with a section to implement programmable I/O. In the case of Actel and Xilinx, these are actual sections of FPGA. With the PSoC, the customizable I/O is a section of programmable digital and analog blocks that can be defined using a graphical tool.

Into this mix now comes the concept being debuted under the name “Tunnel Creek” from Intel. Tunnel Creek differs from the previous examples in that it is a two-chip solution, but one that would easily fit onto a single small module. In Tunnel Creek, the CPU, graphics processor and memory controller are all on the same chip. The only interface to the outside is a x4 PCI Express port. That port can connect to what Intel calls an I/O hub that can support a selected set of I/O options. It can also interface with an FPGA, a proprietary ASIC or other PCIe device that may support selected I/O such as USB, GbE or GPIO, for example. Intel has indicated its plans for an initial I/O hub (and has met some criticism for its initial choice of interfaces) but suggests it may implement more and encouraged third parties to do so as well.

What these developments have in common is that they are addressing the partition problem by trying to put it on a single module with user options for exactly the I/O that meets the application’s needs and no extraneous connectors to take up space. If this phenomenon takes off—and for that it is too early to tell—what will be the implications for board design? Will specific form factors become irrelevant? Imagine a very low-cost design on a single module with only the connectors that are required for the application. While form factor designs will probably crop up to accommodate the ASP approach, designing a custom circuit board will without a doubt become much less expensive and can be justified by lower volumes than before. A one- or two-chip solution on a single module could potentially replace what is today at least a two-board solution for a great many designs. Much of this depends on the relative costs of these new approaches in silicon and on market acceptance. Will third parties flock to the Intel flag? Will the cost and ease of configuration generate acceptance of the Actel/Xilinx/Cypress solutions? These questions will, of course, determine the outcome, but there appears to be genuine interest in the industry for another cut at the partition problem and a real potential for gains.