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EDITOR'S REPORT

New Developments from the Field

Power Analysis Debug, Java and Specs

Just in time for the May issue are some interesting developments—among many—found in expeditions around Silicon Valley and environs.

TOM WILLIAMS, EDITOR-IN-CHIEF

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Are you worried that perhaps your sub-watt processor core is drawing too much power? With an increasing number of CPUs offering more sophisticated power management options, such as a variety of sleep modes and the ability to selectively shut down on-chip peripherals, there is a growing need to correlate and analyze these activities with the application code. Even more options include voltage scaling, clock scaling and partial use of networks. Now technologies are starting to come online that will enable the measurement of power consumption correlated with the execution of the code.

Pioneering this approach is Hitex Development Tools, which has introduced its PowerScale probe with active current measurement (ACM) technology. The PowerScale box connects to the PC with a USB cable and can have up to four probes connected to the system under test. Standard probes measure current ranging from 1mA to 1A, to a maximum voltage of 58V. The ACM probes can measure current as low as 200 nanoAmps up to 500 nA with a maximum voltage of 12V (Figure 1).

Figure 1
Figure 1: The Hitex PowerScale module supports four probes in prallel capable of sampling two different power domains in any combination. The ACM probe (bottom right) is capable of measuring very low currents directly on the processor pins.

PowerScale can be connected to the system using any combination of probes for a total of four power domains that can be measured in parallel. The probes connect to the power supply line and to ground. The probes contain the necessary shunt resistors that fit into the given current range to be measured. Even with the ACM range that covers from 200 nA to 500 nA, the voltage drop is only about 0.1V. Thus even when the current rises extremely quickly, the voltage drop is small enough that the processor can continue operating normally.

In addition to the USB adapter, there is also a power over Ethernet adapter that allows the connection of the probe to Ethernet-powered systems. Hitex offers a graphical user interface that displays the diagnostics of power consumption. The normal PowerScale view shows the current, power and voltage views over a measured time segment. With the additional use of the trigger pin, application events can be collected and shown as markers in the trace. There is also a bin statistic view that answers questions like how much time the microcontroller was in deep sleep mode, what percentage of time the WLAN module was active and more.

PowerScale also provides an open API that will allow PowerScale to be integrated with source code debuggers and other software development tools and tool suites. When this occurs, it will be possible to observe changes in power consumption associated with actual code execution and will open the possibility for the developer to optimize execution for power consumption. For example, if a given segment of code does not require a given on-chip peripheral, that peripheral can be turned off and the power savings measured.

While Hitex does supply compilers and a debugger, its primary expertise is in hardware tools such as JTAG debug tools, analyzers and in-circuit emulation. Partnerships with companies whose primary expertise lies in IDEs and software development tools would be a natural and is something that Hitex is also pursuing.

Another effort in this arena is being pursued by just such a company, IAR Systems, whose Embedded Workbench and C/C++ compilers support a range of processors including ARM, Atmel, Freescale Coldfire, Microchip, ST Microelectronics, Renesas and more. IAR had launched an effort to develop a low-power debugging solution as well, which is to be added to its Embedded Workbench IDE.

IAR is developing a probe technology called J-Link Ultra that will be able to perform analog power measurement to a resolution of 1 mA at a 50 kHz sampling rate. Unlike the PowerScale probe with its two probe options, J-Link Ultra is intended for connection to the board’s power supply pin, which measures the power consumption of the whole system. The probe uses JTAG or serial wire output (SWO) to the probe, which also contains a power sampling subsystem. This enables the instructions that are read by the normal debug probes to be correlated with the timing and measurement of the power consumption.

Currently, the IAR effort is a work in progress on the probe side in somewhat the same way the Hitex is on the debugger side. IAR has the connections to the J-Probe Ultra and its internal power sampling as well as interfaces for debug and power to the Embedded Workbench tool suite, and additional features will be added (Figure 2).

Figure 2
Figure 2: The IAR systems J-Link Ultra samples power levels in parallel with the debug interface and presents the measurements to the debugger. This illustration shows the roadmap for the technology.

Interestingly, IAR Systems also appears to have a partners program that will allow the integration of third-party probes in the future. This could conceivably include such devices as the Hitex PowerScale with its standard and ACM probes that would enable the monitoring of the actual processor power pins along with the board power supply and tight association with the display of the code in the familiar debugger environment rather than an oscilloscope-like display.

Java Improves Multicore Garbage Collection

One of the biggest problems in adapting Java for real-time performance has been adapting the garbage collector so that it does not interfere with scheduling. Garbage collection (GC) retrieves previously allocated sections of memory that are no longer needed by the code. This is a problem made more complex by multicore architectures. Now a newly formed company, Atego, has released Aonix Perc Ultra SMP 5.4 with support for concurrent multiprocessor garbage collection technology. Aonix Perc Ultra SMP responds to the need for multiprocessor and multicore solutions in complex mission-critical embedded and real-time Java applications. 

Aonix Perc Ultra SMP, first introduced in 2008, provided parallel GC that allowed the use of all processors/cores for faster identification and collection of unused objects. A dual quad-core Xeon-based Linux real-time system could collect discarded memory nearly eight times faster than a single-threaded garbage collector but could not run concurrent with other application threads until now.

The new version of Perc Ultra further improves the efficiency of the garbage collection process by implementing concurrent GC. Compared to parallel GC, concurrent GC allows collection of unused objects by multiple processors while Java application threads continue to operate concurrently. Perc Ultra’s GC dynamically allocates available processors/cores to perform garbage collection tasks without disrupting active Java threads on other cores. This enhances the ability of the GC to pace the garbage collection rate to the application’s memory allocation rate.

SFF Starts Searchable Database, Improves USB Channel

A few developments out of the Small Form Factor SIG: The Small Form Factor SIG has set up a searchable product database that allows member companies to document their compatible products and OEMs to search online for products that meet their needs. The database provides classifications for products meeting any of the seven specifications released by the SFF-SIG, and defines eight product categories covering CPUs, I/O expansion boards, mass storage and connectors. Each product listing contains a photo, feature bullets, descriptions and a link to a data sheet in .pdf format as well as a link to the member company’s site.

In addition, the Stackable Unified Module Interface Technology (SUMIT) specification has been upgraded to revision 1.5 offering two improvements. First, it describes the implementation of channel shifting in SUMIT-based systems. Channel shifting in stackable systems means that when an I/O card consumes a resource such as a USB channel or PCI Express lane, it shifts the remaining available resources of a like kind to the pins used by the consumed resource when they are passed to the next I/O card above on the stack. Thus a card that uses USB channel 0 would shift channel 1 signals to channel 0, channel 2 to 1, channel 3 to 2 as the signals are passed up the stack. Each board is assured of a USB port being available up to the number of ports provided. No hardware or software decoding is required.

In addition, SUMIT revision 1.5 describes a simple resource label that conveys the interoperability of a company’s SUMIT-compatible product since all the defined interface signals may not be supplied by a given SBC or I/O module. For SBC cards it shows the resources available and for I/O cards it shows the resources consumed. This provides a quick way for designers to match the labels between I/O cards against the SBC resource label to determine if the required interfaces and power are available.  

Hitex Development Tools 
Irvine, CA. (949) 863-0320.
[www.hitex.com].

IAR Systems 
Foster City, CA. (650) 287-4250. 
[www.iar.com].

Atego 
San Diego, CA. (888) 824-0212. 
[www.atego.com].

Small Form Factor SIG
[www.sff-sig.org].