RTC Magazine

Phase Change Memory or PCM is a new memory technology being explored by several companies. This technology fits between today’s volatile and nonvolatile memory technologies to provide features that appeal to system designers who have had to work around the idiosyncrasies of existing memory technologies for the last several years.

PCM is simple enough to use so designers can begin to forget all the strange work-arounds they must use now to design NOR or NAND flash into their systems. PCM also helps realize some significant improvements in time-to-market as well as related improvements in performance, cost and code density. In certain cases, designers will find it worthwhile to rework existing designs to convert them from flash to PCM. Many designs should also be able to reduce or even eliminate a RAM chip that was once required to compensate for flash’s slow and messy programming protocol.

To help illustrate the strengths and weaknesses of today’s dominant memory technologies against PCM, Table 1 presents the performance of seven key metrics for each of three technologies: DRAM, NAND flash and phase change memory (PCM). Relative performance for each technology is given for sequential and random read and write, power consumption, volatility and cost per bit. 

Why PCM? Why Now?

Why is PCM interesting and why is it now reaching production? There are several reasons for both. The biggest reason that PCM has been unable to make its mark in the market today is that existing memories have proven to be far more economical than any new alternatives. This has been the case for quite a long time, shutting any newcomers out of the market. On any given process, these alternative memories have either suffered from having a larger die size than their entrenched competition, or the wafer processing costs have been significantly higher. Cost is everything in the memory market, so any chip with a higher manufacturing cost doesn’t stand a chance of displacing any existing technology. This will change soon, as PCM costs close the gap with DRAM over the next few years.

On the positive side, there are a few reasons why PCM has recently become attractive. For one, materials have progressed significantly over the past decade and it is now much more feasible to produce the high-purity thin films that are required by the phase change material. Also, there have been numerous breakthroughs with the chalcogenide materials used in PCM because they have been used in high volume to manufacture both CD-R and CD-RW disks. Along with this has been a vast increase in the understanding of the physics of these materials. Process shrinks have played their part: In the past, the amount of material to be heated was relatively large, requiring significant energy to achieve a phase change. As processes have shrunk, what once seemed like an ocean of material to heat has now plummeted to something more akin to a bathtub. Finally, a general acknowledgement that flash memory will soon reach its scaling limit has added impetus to develop follow-on technologies that will continue to scale past this limit. Although flash’s scaling limit has been postponed for a number of years, all flash makers agree that there will soon come a time when flash can no longer be shrunk to the next process node and the industry will have to change technologies.

Figure 1 illustrates the phenomenon behind this scaling limit: the number of electrons stored in a flash bit is on a steady decline. The graph indicates that both NAND and NOR flash could store fewer than 10 electrons per bit before either of these technologies reaches the 10nm process node in about eight years. Ten electrons is far too few to store multiple bits in MLC in a noisy environment, so the minimum required number of electrons is significantly higher than 10, closer to 100 per bit. Even at this level the low number of electrons makes it difficult to meet the reliability requirements of existing applications.

Phase Change Memory is already available. Samsung announced a PRAM prototype in 2004 that is a precursor to impending production. Shortly afterward Numonyx announced a prototype PCM device that started shipping in limited production toward the end of 2008. One other company—BAE Systems—has been shipping its C-RAM chips into the aerospace market since 2006. This market is interested in PCM since it is immune to bit errors caused by alpha particle radiation.

Those designers who have been able to try out these parts report to us that they are pleased to find that the technology removes a number of obstacles they have had to work around when using older, more conventional memory technologies.

To understand the enthusiasm designers have for PCM we must consider how memory is used in the system. A typical system will use both some type of nonvolatile memory for code storage and some type of RAM as a scratchpad and sometimes to store other code. In order to keep the programmer from having to work around the different memory types, operating systems hide the differences between each type of memory and perform the task of managing the volatile and nonvolatile memories in a way that is transparent to the other programs. This adds a considerable amount of complexity to the system.

Even with this help, the programmer is under some constraint to fit the code into the read-only code space and the data into the read-write data space. If either code or data grows larger than the size of its memory, even by a single byte, the size of that portion of memory must be doubled at a significant price increase. In some cases this can be avoided in a PCM-based system.

Phase Change Memory has changed the rules of the game. No longer must code and data be split between two fixed-size banks of NVM and RAM. Code and data may be contained within a single component. For small system designers this reduces chip count and power consumption. Designers of both large and small systems will appreciate the fact that there is no longer a fixed delineation between read/write and read-only memory.

Intricacies of Flash

Flash memory is difficult to manage. One designer we interviewed referred to the process of managing flash as a “very involved dance.” Those who have designed with either NAND or NOR flash will attest to this. Flash management involves a number of considerations like wear leveling, read-while-write and bad block management that make this task extraordinarily complex.

Phase Change Memories present considerably fewer problems than do flash designs. PCM is byte-alterable so there are no erase blocks as there are in both NAND and NOR flash. This vastly simplifies writes. Writes do not need to be preceded by an erase cycle—in PCM ones can be changed to zeros and zeros can be changed to ones. A PCM’s write is more like a write to a RAM than to either NAND or NOR flash.

PCM has fast write cycles with no need for the erase required by NAND and NOR. This removes the need for a concurrent read/write capability, and programmers will rarely, if ever, need to write code to prevent reads from occurring near a recent write.

PCM has random NOR-like or SRAM-like addressing that perfectly matches what the processor wants to see. Furthermore, PCM does not require the error correction used with NAND flash since all bits are guaranteed to contain the same data that was written into them.

All the algorithms that are required to manage flash with wear leveling and bad block management are quite simply unnecessary in a PCM environment. Some call PCM: “A firmware/software engineer’s perfect nonvolatile memory.”

There is also a benefit to the programmer, since the boundary between code and data space is more flexible than it has been. In today’s designs each memory application requires its own unique memory topology, commonly:

• NOR and SRAM

• NOR plus NAND and SRAM or PSRAM

• NOR or NAND plus DRAM or mobile SDRAM

 These systems rarely use the nonvolatile memory to store temporary data, and can never use the RAM to store code, since the contents of the RAM disappear upon power loss. PCM helps to simplify these configurations. A single PCM chip or a PCM-only array will store both code and data, often removing the need to pair a RAM chip with a nonvolatile chip.

As an added bonus, the programmer need now worry only about the size of the code plus data, rather than about the code space and the data space as two separate areas. If the data space increases by a couple of bytes, perhaps there will be room that can be “borrowed” from the code space. This luxury is simply unavailable in a non-PCM topology.

How PCM Works

Phase Change Memory uses the changing state of a special material to determine whether a bit is a 1 or a 0. The phase change memory’s two states are “crystallized” and “amorphous.” Like a liquid crystal display blocks light or allows it to pass through, depending on a crystal’s orientation, the chalcogenide glass that is used for bit storage in a PCM either allows current to pass (when crystallized) or impedes its flow (when amorphous).

Bits are changed from a crystalline state to an amorphous one via a tiny heater at each bit location that melts the glass then cools it in either a way to allow crystals to grow or to keep crystals from growing. A set pulse,raises the temperature to melt the glass and holds the temperature at that level for a time, ramping it down once crystallization has begun. A reset pulse quickly raises then lowers the temperature before the melted material can form any crystals. This results in an amorphous, or nonconducting, organization of the material at that location (Figure 2). 

Since very small heaters are used, they can heat the material very rapidly for a tiny location—on the order of nanoseconds. This allows fast writes to be performed and prevents adjacent bits from being disturbed. Furthermore, these heaters shrink along with process geometry shrinks, which will make parts produced with a smaller process easier to program than their large-geometry predecessors. This technology is expected to shrink well beyond the limits of NAND and NOR flash (Figure 3).

Speeds are comparable with flash today and will later approach the speeds of DRAM.

From a system architecture viewpoint, one beauty of PCM is that there is no block erase—each bit can be set or reset at any time independently of all the other bits. This gets past the limitations that block erase imposes on both NAND and NOR flash.

Memory chip prices are highly dependent on production costs, and Objective Analysis projects that PCM makers will take steps to bring their costs down to those of competing technologies.

Today PCM sells for roughly 25 times as much per gigabyte as does DRAM, but PCM uses smaller cells than do leading-edge DRAMs, so PCM manufacturing costs should be able to fall below those of DRAM, once wafer and process equality is reached. As the technology gains parity with DRAM in process geometry and wafer diameter, and as unit volume grows large enough to impact economies of scale, PCM will cross below DRAM’s average price per gigabyte, a situation the market should expect in 2015-16. Further cost reductions will become possible as PCM migrates to multi-level cells, when the technology’s cost can be expected to fall to less than half that of DRAM, making it the second least expensive technology after NAND.

It is not too early to start paying attention to phase change memory. We know that flash is approaching its inevitable scaling limit, and that some other technology like PCM will eventually take the place of flash. PCM makers indicate that this technology will reach price parity with DRAM in the middle of the decade, a change that will start a whole new way of thinking about memory system design.  

Objective Analysis.
Los Gatos, CA. 
(408) 356-2549.
[www.objective-analysis.com].

Numonyx.
Folsom, CA.
(888) 466-8666.
[www.numonyx.com].

Samsung Semiconductor.
San Jose, CA.
(408) 544-4000.
[www.samsung.com].