RTC Magazine

As embedded applications become more responsive to their environments, the number of peripherals needed to capture and process data is exploding. It is commonplace for microcontrollers to have ADCs, DACs, PWMs, multiple timer/counters and numerous TWI, SPI, CAN, USB and USART interfaces for communications. More peripherals mean more cycle-intensive interrupts, and the amount of data that must be moved between the memories and the peripherals grows exponentially.

Generally, the CPU is in charge of processing interrupts and moving data. In some applications the CPU may spend most of its cycles on these activities. For example, managing two simultaneous inter-peripheral communications and a single 64 Mbit/s data transfer would require 200 CPU MIPS and consume 240 mA due to the extensive context switching and interrupt usage involved. In order to meet the extra computational load, the CPU clock may have to be increased, with a linear increase in power consumption. In extreme cases, the design must be migrated from an 8-/16-bit to a 32-bit device, just to keep up.

Frequently, a signal on a peripheral does not in itself require the CPU to do anything except let another peripheral know it needs to do something. Unfortunately, liaising between two peripherals requires cycle-intensive interrupt processing. For example, in a motor control application, overheating is prevented by constantly measuring the current on the motor and toggling an analog comparator when an over-current situation signals that the motor has stalled. The CPU is interrupted and shuts down the pulse width modulator (PWM) output for the motor driver. This process can require tens of cycles plus another 20-100 cycles to restore the context. The microcontroller is not really doing anything that requires its processing capabilities. It is basically just passing a message from an analog comparator to a PWM output. The cycles are basically wasted.

Other cycle wasters include the use of timer/counters to time other peripherals such as ADCs and DACs. In these situations, an interrupt is generated to start every conversion. At a sample rate of just a few kHz, these timer/counter interrupts consume over 1 MIPS—about 8% of a 12 MIPS MCU’s capacity.

If these peripherals could communicate with each other directly without interrupting the CPU, millions of cycles could easily be saved each second. One reason why 8-bit applications outgrow 8-bit microcontrollers is that, as applications become more data-intensive and interrupt-driven, most of the MCU’s MIPS are wasted on these activities. Transferring data between the peripherals and memories further increases the load on the MCU. A 350 Kbit/s data transfer requires between 22 and 25 CPU MIPS.

One solution to this problem is to use a low-power 8/16-bit single-cycle RISC MCU with an 8-channel event system and DMAs that off-load these functions from the CPU. This microcontroller architecture allows the simultaneous execution of up to 8 inter-peripheral events, plus up to four 64 Mbit/s data transfers, while consuming a total of less than 10 mA. Since the event system and DMA allow the peripherals to communicate with each other autonomously, no CPU clock cycles or interrupts are required. The CPU can be put into sleep mode.

The event system routes peripheral signals through a dedicated network outside the CPU data bus and DMA controller. The benefit of this is predictable and latency-free inter-peripheral signal communication that reduces CPU time and frees up interrupt resources. The event system enables a change of state in one peripheral to automatically trigger actions in other peripherals. In the motor control example cited earlier, an analog comparator, timer/counter, I/O pin or ADC in the microcontroller can directly shut off the PWM for the motor drive within two cycles of an over-current situation, offering better protection for the motor, while using zero interrupts and zero CPU cycles (Figure 1).

Peripheral events that can trigger the event system include timer/counter compare match or overflow, analog comparator toggle, pin change, ADC complete or compare and real-time counter overflow. Events that can be triggered in other peripherals include ADC or DAC conversion, input capture to time stamp communication or ADC measurements, external frequency or pulse-width measurements, clocking of timer/counters, starting a DMA transaction or changing a pin output.

Deciding which events should trigger which actions on which peripherals is fully configurable and completely up to the designer. Event system configurations can be kept static and locked, or can change dynamically during various stages of the application execution. The event channels operate in parallel and up to 8 pairs of peripherals can be interconnected simultaneously at any time.

Using an event system removes the bottlenecks associated with multiple and/or frequently triggering interrupts. There is no software overhead and critical tasks can be performed independently of the CPU. The implications for power consumption are significant. A conventional 8-bit MCU, without an event system, requires about 16 MIPS to shut off a PWM in response to an over-current condition on a motor. At 16 MHz, 1 MIPS/MHz, and 0.6 mA/MHz, the microcontroller would consume 8.6 mA for this task alone. A comparable MCU with an event handler would require zero MIPS and no incremental power consumption (Figure 2).

By eliminating the interrupt, processing response latency can be reduced to a guaranteed maximum of two clock cycles—or 62.5 nS with a 32 MHz clock. The fastest possible response time is 31.2 nS. In fact, using an event system on an 8-/16-bit MCU can achieve event response times that are 37 times faster than that available from a conventional 32-bit MCU without an event system (Table 1).

Souping up Data Transfer

Transferring data is another cycle-intensive contributor to power consumption. Since an 8-bit CPU, on its own, can transfer only one byte of data at a time, there is a lot of processing overhead involved. An 8-bit microcontroller must execute 22 MIPS and consume 14 mA to effect a 350 Kbyte/s data transfer. SPI and USART transfers can have data rates as fast as 25 Mbit/s, making it virtually impossible for a typical 8-bit MCU to support the maximum rate.

Adding a peripheral DMA controller to the device offloads essentially all these cycles from the CPU. When the CPU data bus is free, the DMA controller uses it to transfer data between the memories and peripherals without using CPU resources. The internal buses to the peripheral registers including I/O pins, memory mapped EEPROM, internal SRAM and the External Bus Interface are split to enable simultaneous bus access from the DMA controller and the CPU. Hence there is always a communication channel available for the DMA. Transferring 350 Kbyte/s of data with a DMA controller requires 99% fewer MIPS and consumes less than 1 mA, compared with 22 MIPS and 11 mA for an 8-bit MCU without DMA (Table 2).

The DMA controller can move data from a peripheral register to internal or external SRAM, between SRAM locations, and even between peripheral registers directly. The four DMA channels have individual priority, source, destination, triggers, addressing modes and transfer block sizes. The DMA can transmit from 1 to 16 Mbytes in a single transfer, due to the simple linear data memory address space in the RISC CPU and to the auto increment/decrement and reload features in the DMA controller.

Using the event system in conjunction with the DMA controller, an analog-to-digital and digital-to analog conversion can be achieved as follows: A pin-change on any I/O pin or an overflow on any timer/counter triggers the ADC conversion without any CPU cycles. The ADC conversion result is transferred over a DMA channel to the SRAM. At the same time, a second timer/counter can trigger a high-speed DAC conversion using a second DMA channel for the data. The event system can make the analog comparator trigger input capture for 100 percent accurate time stamps, automatic capture to time stamp the beginning of communication transactions, or ADC conversion scans on the second ADC. Four event channels are still available that can be used for fault protection of a PWM output controlling a high-voltage driver stage, cascading of timer/counters, and a couple of communication channels—all at the same time, while the CPU is sleeping (Figure 3).

Adding an event system and DMA to a microcontroller can have an enormous impact on power consumption. In some applications, the MCU can spend most of its time in sleep mode, consuming as little as 80 uA/MHz while all peripherals can continue to operate. In a hypothetical application with eight simultaneous events and four 350 Kbyte/s data transfers, an 8-/16-bit MCU with an event handler and DMA would be able to spend 31.6 million cycles per second in sleep mode and would consume a total of just 4 mA. Any traditional 8- or 16-bit MCU without an event handler and DMA would consume 52 to 60 mA. A 32-bit MCU would consume 34.8 mA—almost 10 times more power. In an application with extensive interrupts and data, a microcontroller with an event handler and DMA would consume 90% less power.

Atmel
San Jose, CA.
(408) 441-0311.
[www.atmel.com].