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Powering Up COM I/O Boards

Interoperability Scores a Victory with Plug and Play COM Spec

Working Groups collaborate to release new COM specifications for COM/carrier board compatibility.

ARNOLD ESTEP ADLINK

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Computer-on-module (COM) manufacturers are delighted that their pluggable module alternatives to conventional single board computers (SBCs) are getting attention beyond the high-volume gaming and kiosk-type applications for which they were initially well suited.

Governed by industry standards, the well-defined, feature-rich, high-density connector interfaces of COMs have attracted widespread interest from former SBC strongholds including industrial, medical, avionic, and even military applications. Plug-and-play CPU cores would reduce supply risks and extend system lifecycles. Before victory can be declared, however, the interoperability of COMs must be greatly improved. Only then can system OEMs realize the promises of multi-sourcing and future upgradeability.

Systemic Challenges

The COM architecture, which combines a custom carrier with an off-the-shelf processing core, provides efficient customization for projects that lack the time or resources for a custom single board computer. It fits most system integration projects with production volumes from 500 to 10,000 units per year. The COM approach has many advantages over full custom designs, including reducing scope and engineering complexity and speeding time-to-market. The average time to design a carrier board is usually less than half the time of a full custom OEM board. An example COM is shown in Figure 1.

The concept of a small CPU core on a standardized module sounds simple. The carrier board provides power, and the COM contains the processor and chipset that already provide built-in buses and I/O back to the carrier. Conversely, SBCs bring I/O to pin headers and expansion buses to standardized interfaces like PC/104. So consolidating all of these signals into high-density surface-mount board-to-board connectors seems like just a logical extension of the other architecture.

Unfortunately, the resemblance ends right there. For starters, buses and I/O are well-defined, but carrier design considerations must include logic levels (5V, 3.3V, 2.5V, etc.), terminations and pull-ups. The major problem is that instead of the case where SBCs have power supplies on board that meet the voltage and current requirements of the CPU and chipset residing on the same board, a COM requires each application-specific carrier board to satisfy its CPU and chipset power requirements on a different board. Worse still, “black-box” modules are designed with varying bulk capacitance, power sequencing, and Advanced Configuration and Power Interface (ACPI) power management support.

In order for a COM Express module to function properly, the entire interface must be terminated with proper signals, timing, sequencing and circuits (Figure 2). Suddenly, designing a carrier board resembles a 9-inning ball game. If the engineer can’t get the carrier to operate with the first vendor’s module, another round is necessary, quickly becoming a twilight double-header. Whether designing in-house or farming out to a design services company, OEMs counting on multi-sourcing are wise to confirm interoperability early in the design phase.
Releasing a system to production with only one module validated can lead to unpleasant surprises later when the purchasing manager needs an emergency second source due to supplier delivery or quality issues. Too often, the next vendor’s module won’t boot, and there are many possible reasons why. The designer is locked in the clubhouse without any visibility, and the BIOS and OS offer few clues about where the replacement “black box” module hangs.

The interoperability problems are well documented in the COM vendor community. Often, the vendors create straightforward implementations to the module standards only to have customers encounter interoperability issues. The situation transcends any one vendor, so it has been bounced back to Spring Training for the originating trade groups to sort out.

Responding to calls for help, two groups are tackling the obstacle to growth head-on: PICMG and SFF-SIG (Small Form Factor Special Interest Group). PICMG’s approach must work within the confines of the existing COM Express specification, to minimize disruption to the growing market for legacy-free COM Express modules. SFF-SIG approaches the challenge with a ground-up new architecture that is both legacy-friendly and forward-looking to USB 3.0 and PCI Express 2.0.

The PICMG organization has completed a year-long task of generating a large document called the Carrier Design Guide (CDG). The CDG contains reference circuits and detailed explanations to help OEMs and design services companies implement typical peripherals on the application-specific carrier board designs. PC architecture buses such as PCI Express, PCI, LPC and SMBus can be extended to support other peripherals for diverse industrial applications. CDG complements the COM.0 specification for COM Express modules without substantially affecting COM.0. Many of the COM Express vendors are redesigning their reference carrier boards to comply with CDG, which will greatly help interoperability. CDG can even improve the consistency of new module designs in the future.

Part of that consistency involves managing power. The industry-standard ACPI specification defines power-saving levels when the system is not operating, but implementation across COM Express modules has been inconsistent in the past. CDG addresses this point by defining the state of the many power rails that may be present in the system, including the standby nets that are powered when the main rails are at zero volts. In addition, suspend status signals and wake-up events are defined more thoroughly. CDG describes how to provide power to peripherals so that they continue to operate as desired during the suspect and soft off states. After all, these peripherals and part of the Southbridge must stay awake while the rest of the system is off. A system that won’t wake up again is not particularly useful.

A philosophical debate among COM suppliers is how to implement serial ports and other “legacy” peripherals within an architecture that is promoted heavily as “legacy-free.” CDG cautions carrier designers about the limited support for the Low Pin Count (LPC) bus for such peripherals, and PICMG takes a neutral stance with regard to vendor offerings “under the table” as initialization of carrier LPC devices is heavily intertwined with the BIOS on each vendor’s product. Instead, CDG suggests the use of the driver-loading plug-and-play model of USB, PCI and PCI Express devices for serial ports and other legacy ports.

CDG contains all of the tricks of the trade that designers can deploy for a winning carrier board, including coupling capacitors, bypass capacitor types, bulk capacitance on power and standby rails, pull-up resistor values, series and parallel terminations, ferrite beads, reset circuits, and even more. Future challenges will include trying to layer USB 3.0, PCIe 2.0 and DisplayPort signals on top of the five existing pinout types.

SFF-SIG Steps up to the Plate

Next to bat, the Small Form Factor SIG wants to see the rugged markets served well with an all-in-one ground-up new COM architecture. Offering a fresh roster of new modular embedded computing specifications, SFF-SIG aims to tightly control COM implementations to reduce or eliminate the need for carrier design guides beyond the module vendors’ own reference schematics. Interoperability-by-specification is a noble goal that time will have to test.

SFF-SIG’s new standard is called COMIT. The acronym stands for Computer On Module Interconnect Technology and is pronounced “com-it.” COMIT is a modular, high-speed connector system composed of the most common high-speed and legacy interfaces available from modern low-power chipsets (Figure 3). The purpose is to provide a compact, interoperable processor core connection architecture for future embedded systems designs. A legacy PATA/IDE interface connector is optional, and purposely left without other features so that it can “go away” by itself without compromising other features once SATA drives and SATA and/or SD SSDs fully replace their IDE counterparts in the embedded market over time.

COMIT addresses the emerging need for a COM standard that utilizes multi-sourced, state-of-the-art 10 GHz connector technology and focuses on new and future bus technology. Ensuring interoperability between COM modules is also an overriding concern. Longevity has long been the promise of COM products, and the ground-up new signaling optimized for ultra-low-power processors such as Intel’s Atom family and VIA’s Nano processors is an important future-proofing step forward for COMIT. Power and signaling levels are two major areas of focus for interoperability.

To address power, ample power and ground pins are utilized for the supplies on COMIT. Thirty-seven grounds and 21 power pins are included for power, high-speed signal returns, impedance matching and control of EMI emissions and susceptibility. The additional power and ground pins are an absolute necessity as interface speeds increase. Power control adheres to industry standard ACPI “ATX-style” signaling conventions. This eases module power control and ensures that all voltages necessary, except the standard 3.3V, 5V and 12V supplies, are generated on the processor module. This further minimizes issues with power supply sizing and stability that occur when passing these processor-specific power rails across a connector. Suspend and battery voltages are also provided to the connector.

Another area that can cause cross-compatibility problems is the logic high level. A particular processor may specify that a signal is capable of only 2.5V, but an older carrier board may have this signal terminated or driven to 3.3V, causing reliability problems or failures. To mitigate these issues all control signaling across the 240-pin COMIT connector must be 3.3V tolerant. There is no wiggle room in signal definitions. Also, all input termination is included on the processor module, whether the feature is included or not. If a COMIT processor does not include a certain function, the module is required to include termination where necessary to ensure there are no floating inputs to the baseboard for all COMIT interfaces.

Tightly Controlled Sequencing

The COMIT Specification defines power sequencing requirements to ensure module reliability and cross-compatibility. As shown in Figure 4, the real-time clock battery voltage must be up first, then +3.3VSB (standby) must come up or be already up, then the main 5-volt supply can come up, followed by the assertion of PWRGOOD (power good). Powering down proceeds in the reverse order. Compliance with this requirement prevents the lockups and erratic behavior of some COMs on the market today that are plugged into other vendors’ reference designs.

The SEARAY connector from Samtec provides high speed, high pin density and ruggedness. It is a 240-pin high-density (0.050” pitch) connector pair. Samtec and Molex are already cross-licensed to produce the SEARAY connector series, providing longevity for mil/aero, medical and industrial applications. The chosen connector system is capable of a differential signaling rate of 9 GHz bandwidth (at -3dB insertion loss) to support current and future high-speed signaling (Figure 5).

COMIT supports several common interfaces for low to moderate speed expansion requirements. Industry standard serial interfaces include SMBus, I2C, SPI, Microwire and a UART. SMBus alert is included for power management alert functionality or general SMBus interrupt usage. Two chip selects are included for SPI/uWire, which can be expanded within the target device to any number needed. SPI and SMBus are defined as 3.3V signaling. Five-volt tolerant devices may be used as long as they do not drive the SPI signals on the bus beyond the 3.3V nominal specification. The UART signals are defined as 3.3V only. Level translators must be on the baseboard where needed.

To handle cases where the particular COM doesn’t happen to support a feature defined at the interface, the COMIT Specification dictates that all features on the connector not used by the processor are terminated inactive where necessary on the processor module. This ensures that there are no floating inputs to the baseboard and no issues with unused features for the carrier designer to deal with. For the opposite scenario where a module’s feature is not terminated on the baseboard, the COMIT Specification dictates that processor modules handle all input termination themselves. This ensures that there are no floating inputs to the processor module and no issues with unused features, which could lead to reliability and determinism problems.

While CDG and COMIT are thorough in providing COM designs for interchangeability, it is absolutely essential to use each module vendor’s documentation in order for carrier boards to be designed properly. This includes analyzing multiple vendors’ products up front. It will take some time for the consistencies presented by CDG and COMIT to result in truly interchangeable COMs and carrier reference designs. To learn more, visit www.picmg.org and www.sff-sig.org. The aforementioned trade groups and their members have served the industry well in the publication of these landmark specifications and in steering COM vendors toward interoperability. 

ADLINK
San Jose, CA.
(408) 360-0200.
[www.adlinktceh.com].