TECHNOLOGY IN CONTEXT
Microprocessors Adapt Performance to Stay Cool
The newest microprocessors from AMD, Intel and Via adapt performance parameters to match real-time energy constraints in embedded systems. Via’s “Adaptive PowerSaver” technology has been enhanced on the company’s Nano processor.
J. SCOTT GARDNER, ADVANTAGE ENGINEERING
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The x86 processors have gotten smarter about power management, and embedded systems won’t ever be the same. With fewer transistors, RISC chips appeared to have an unassailable technical advantage that x86 and its architectural baggage would never overcome. Why are the RISC chips now battling x86 for the heart and soul of the embedded market? Setting aside the cost improvements and market shifts that exploded demand for PC functionality in embedded form-factors, a number of technical issues are eroding RISC’s advantage in power consumption.
While it is true that the inherently simpler RISC designs require fewer transistors, the newest x86 CPUs are able to reduce active and static power losses by enabling smarter power-control algorithms that adapt processor performance and power consumption to match real-time software workloads. With adaptive power management, embedded system designers can create products that dynamically match CPU performance to thermal, electrical, acoustic and physical design constraints. This holistic design approach brings a greater degree of flexibility and cost savings from design reuse, since a single compute platform can scale up and down into multiple products.
An adaptive system uses feedback to modify itself and match the needs of the system being controlled. Early efforts at PC power management introduced “operating system directed power management” (OSDPM) to direct the CPU and peripherals into lower-performance (and lower-power) operating and idle states. Often called “dynamic power management” (DPM), many embedded products employ a similar approach. ARM customers can license the Intelligent Energy Manager to monitor software workloads and control CPU performance and power consumption. While workload monitoring is a good first step, an adaptive power-management system puts the CPU itself in the middle of a control loop that adapts CPU parameters in response to real-time changes in the power environment. Many customized RISC-based designs undoubtedly employ some of these sophisticated power-control techniques, but the new x86 CPUs are deploying adaptive features on high-volume standard products.
Embedded system designers can examine Via’s Nano CPU to analyze the future of adaptive power control. Even for designers considering other x86 or RISC CPUs, the flexibility of Via’s features offers insight into how this technology will evolve. The company first introduced Adaptive PowerSaver on C7-M processors, but its high-performance flagship, Nano (see sidebar: “The Nano Processor”), has extended the technology to include more real-time CPU control. Adaptive PowerSaver consists of control system features for both P-State control and thermal monitoring. P-States (performance states) define a range of operating frequencies through which the operating system can shift in response to changing workloads (Figure 1). Basic thermal monitoring allows the CPU to automatically throttle back performance if on-die sensors detect high temperatures. Every CPU vendor is tweaking P-State control and thermal monitoring, but Via’s Centaur design team has always focused on power efficiency. The CPU designers were early to recognize that P-States and thermal monitoring were mechanisms that facilitate the inevitable shift to adaptive control of CPU parameters in a real-time environment.
P-State Control in Adaptive Systems
P-States are static tables that are stored as pairs of bus multipliers and voltage IDs (VIDs). The table is organized with state “P0” defined as the highest-performance state. At manufacturing time, CPU vendors guarantee that the CPU will operate reliably at every combination of frequency and voltage in the P-State table. While the operating system has information about the software workload and can direct the CPU into a lower-performance state to save power, system software cannot react fast enough for real-time optimization in response to changes in the thermal environment. To ensure real-time performance and protect the CPU from damage, the adaptive control system executes on the CPU in dedicated hardware. The P-State table is defined to guarantee performance at the worst-case thermal design point (TDP). CPU on-die sensors provide feedback to adapt the P-State parameters and take advantage of real-time thermal headroom.
Adaptive PowerSaver technology includes a number of flexible features to allow system designer control over how the CPU adapts to take advantage of thermal headroom. If the CPU drops below a factory-defined temperature, then an adaptive control system can take advantage of that thermal headroom to either save power or improve performance. If saving power is more important than performance, Via’s Adaptive P-State Control can be enabled to automatically shift to a lower voltage while keeping the same P-State bus multiplier.
Via engineers like to describe this as “parallax,” since the entire P-State table is shifted to the left when the CPU is operating in a system with thermal headroom (Figure 2). The voltage is shifted down by an offset value that is set at manufacturing time. Without Adaptive P-State Control, a CPU would waste power by running at the voltage required on the worst-case performance line. Instead, the CPU is able to transparently deliver identical performance at lower power consumption. Keep in mind that thermal headroom may be a response to a lower software workload. Long before system software could detect the new workload and signal a P-State change, the adaptive control system on the CPU could start saving power. Figure 2 also highlights the use of an “inflection ratio,” mapping P-States to closely match the device yield curve and allow better performance efficiency than the simple linear mapping shown in Figure 1.
Instead of using thermal headroom for lower power, a technique called Adaptive Overclocking allows a performance-focused approach to adaptive power control. If the CPU measures a temperature below a factory-configured threshold and Adaptive Overclocking is enabled, the CPU will shift to a higher-performance P-State automatically (Figure 3). The higher P-State will have an accompanying increase in power consumption, but the system improves performance to the limits of the real-time thermal environment. Note that the overclocked P-State may not necessarily require a higher voltage. Other x86 vendors are introducing similar “turbo mode” features for high-end PC microprocessors.
Via has disclosed a lot of flexibility in Adaptive Overclocking technology, though some of the extra options may not arrive until later versions of Nano. The system software is allowed to choose how P-States transition when thermal headroom allows a boost in performance. The P-State table can be structured with P0 corresponding to the “turbo” speed, while slower P-States get used when the CPU is running hot. If the user wants P0 mapped to worst-case power, special turbo P-State registers are provided that store performance settings for the times when the CPU is running cooler. It will be interesting to see how embedded system designers implement their systems.
Thermal Monitor Control in Adaptive Systems
Thermal monitoring has evolved beyond simple Stop/Grant throttling, referred to now as TM1. On CPUs that support dynamic voltage scaling, a TM2 mode was defined that throttles performance by shifting to a low-frequency state with an accompanying lower voltage. The throttling was originally defined to keep thermal transients from exceeding the maximum CPU case temperature. Embedded system designers often use CPU throttling as a form of adaptive power control in thermally constrained systems. Via has introduced Adaptive Thermal Control, and also describes the new features as TM3 to highlight the differences from TM2.
Adaptive Thermal Control adds user control of the thermal threshold for throttling. This allows system designers to tune the thermal environment within specific constraints, knowing that the CPU will automatically take advantage of all available performance. Adaptive control goes a step further by keeping the CPU speed at the maximum level allowed by the thermal setting. This is more responsive than TM2, which always drops to a minimum performance state until the CPU cools down.
With Adaptive Thermal Control, embedded system designers gain some interesting capabilities for managing design constraints. While there is an obvious benefit to guaranteeing the maximum heat produced by the CPU, system designers can also use Adaptive Thermal Control to control other system variables. For example, if the thermal environment is well understood, then a system designer also gains the ability to control the maximum CPU electrical current. If the system constraint is acoustic, then the CPU performance could be directly controlled by adjusting fan speeds. The CPU would run at the highest performance possible within the acoustic noise budget. With an adaptive system, the CPU automatically provides the maximum performance within the design constraints being used as a control variable. Design reuse becomes a huge cost saving, since a single design with performance headroom can be tuned to fit into multiple products. Embedded system designers will certainly find many interesting applications for this capability.
Looking into the near term, there are some announcements on the horizon. Via wasn’t yet ready to disclose a new adaptive control feature to maximize performance while maintaining a constant battery life. Instead of controlling for maximum power consumption, this technology will adapt performance for a maximum average power. This will add a new dimension in adaptive power control and should be a welcome innovation for mobile systems. Via also plans other near-term power-management enhancements that will be introduced on its Nano processor.
Taking a longer view, adaptive power management will become pervasive on all CPUs. The designers will begin to control more performance and power parameters than just frequency and voltage. Chip designers already power down portions of the CPU during sleep states, but they may begin to dynamically control power during the operating state (C0). A simplistic example would be to turn off or reduce the frequency and voltage to the floating-point unit in slower P-States. This type of control may introduce latency to P-State transitions, but the active power savings may be substantial. Power management will need to become even more sophisticated. Adaptive power control will present increasing challenges to operating system developers, since power control algorithms need to run in real time and be very close to the CPU. Embedded system designers are very experienced in these real-time issues, and embedded systems engineers may be the ones to drive the next wave of x86 innovation.