RTC Magazine

The connectivity needs of industrial, automotive and consumer computing continue to grow to encompass everything from USB to PCI Express (PCIe). Unlike component-level solutions, System-on-a-Chip (SoC) technology has the ability to integrate multiple connectivity solutions on a single silicon chip, cutting development cycles and costs while increasing product functionality, performance and quality. As a result, embedded designers are more often integrating connectivity and high-performance processor IP on the same SoC. However, this connectivity integration has to be universally accepted, processor agnostic and have the ability to remove bottleneck constraints. Emerging next-generation standards, such as PCIe Gen2, add to functionality, performance and quality demands. As such, embedded designers face great challenges in balancing integration of appropriate connectivity blocks while maximizing performance for highly competitive consumer, industrial, automotive and other verticals.

Among all options, USB is probably the most versatile and successful connectivity standard in computing history, in regards to addressing multiple vertical segments. It has been implemented in PCs, peripherals, digital imaging, audio, video, wireless and wired networking, storage, automotive, industrial, home-automation, mobile phones and more.

Franchising a Platform for Connectivity

It stands to reason that with so many connectivity variables available in a product design, perhaps “franchising” a platform where only small changes are needed to implement such varieties might be ideal. The key concept behind franchising an embedded platform–dubbed Franchisable Embedded Platform (FEP)–is the ability for integration that addresses multiple verticals within a single SoC. Consider FEP as a one-time investment, from the viewpoint of an ASIC and a system, in capturing specific vertical segments with your brand. With FEP, you can quickly enable the repurposing of existing designs to suit new connectivity needs. FEP will help designers meet the latest connectivity requirements and turn around new designs within a limited marketing window. FEP can also aid in meeting price targets and maintaining system performance and compatibility with industry standards.

The concept is especially effective as it relates to marrying various connectivity options on a SoC to better meet integration challenges. For example, if we pick a popular connectivity standard like USB to start with, we can connect with almost all key market segments (PC, consumer, industrial, etc.). Now, if we keep adding other connectivity blocks one at a time, we can more specifically target a market segment. In this conceptual way we can attain a true franchisable embedded silicon platform to meet multiple market segments, because with an incremental change in system design, we can have a number of systems to suit a number of markets.

FEP can greatly optimize the process of spinning new SoCs for every vertical. All four major stages of designing an SoC–specifications, integration, verification and implementation–are virtually eliminated.

Designing Connectivity with FEP

The base design must be done with multiple considerations in mind: appropriate market research and trade-offs for every vertical segment, their required performance turnaround time, a review of the overall benefit of the integration, and target cost. Selective integration of functional blocks is the key to creating the SoC that can address differing vertical segments with incremental design modifications at the FEP level. For example, if you created a system with Ethernet to PCIe, and you later come to realize a new market requirement for Ethernet to USB, FEP makes it possible to reconfigure the existing device with EPROM and a few physical connectivity changes to quickly arrive at a new design.

Another key consideration while dealing with connectivity is the protocol standards. These include the implementation of the logical link layer, MAC layer and physical layer. Now, the goal is to get the best possible design from the integration of multiple connectivity options using multiple standards on a single platform. Implementing this at the board level defeats the purpose of FEP, and so a wiser choice is to implement them on one single die so that options like USB, Ethernet, PCI, PCIe, ISA, GPIO, etc. are on one single die (Figure 1). Such SoC connectivity can be stand-alone or put together around an embedded processor, such as an ARM 9. Having all these pieces on single die will eliminate most delay issues, enhance signal integrity, add data crossover security, improve design-in time, add design stability and will address many other marketing and business-related issues (Figure 2).

The designer should be able to create multiple applications merely with an EPROM configuration for the specific crossover bridge such as a USB to PCIe connectivity application or to 10/100/1000 Ethernet to USB with this base platform. Now, one platform can be franchised across whatever connectivity options need to be addressed today or tomorrow.

The key purpose of FEP is to reduce integration risk and accelerate time-to-market. However, to benefit from FEP’s ability to accelerate time-to-market, FEP must be approached from a holistic view of silicon to systems.

Industrial, business and consumer applications seem to be most ideal for an FEP-based implementation. These are volume digital data, file server, NAS, printer server, SOHO, docking stations, display, and many others. These applications could very easily use combined high and low bandwidth features of USB or PCIe. Such combinations of features can address multiple applications using the same design. However, with USB to Ethernet, bandwidth requirements at the back end do have to be higher to alleviate network bottlenecks, and an Ethernet 10/100/1000 port should be incorporated as part of the solution.

Standards-based I/O functional blocks will require no additional circuitry. System designers should be able to create various functional modules (such as wireless, NAS, etc.) that could later make up a readily available ecosystem to be used to address a number of applications.

With a quick replacement of one functional block for another, or replacement of a peripheral card to accomplish new specific functions, moving into a different domain-specific area can be accomplished quickly when an opportunity arises, such as with the upcoming PCIe Gen2 or USB 3.0 standard. Source code compatibility will also contribute to ensuring a fast time-to-market, since given the base design, lengthy code modification should not be required.

Multiple Interfaces on SoC

Connectivity in embedded systems has become a defining item of a system. As we look at the standard SoC versus FPGA, FPGA is a limited FEP solution for multiple reasons. Design-in cycles, tools and time-to-market for systems and ultimately costs are some key obstacles with an FPGA as an FEP. Designing with FPGAs brings multiple design-in overhead activities, such as the use of complex tools noted above, along with platform choices, added IP considerations, extra tools and design-in assistance–all of which affect turnaround time.

In contrast, if you choose a dedicated off-the shelf SoC processor to enable the required function at maximum capacity, it can be done without the burden of aforementioned overheads, which in turn allows your designs to remain competitive in a crucial time-to-market industry like connectivity. It allows OEMs to address their target vertical segment economically without sacrificing performance, features, or marketing window and with the capacity to spin next-generation products in very little time. Figure 3 shows an example FEP implementation of a network appliance processor with multiple USB host and OTG ports along with other connectivity options.

This device has multiple key interfaces that include PCI, 10/100, USB, Serial, Parallel and GPIO to address multiple key market segments. With the FEP concept employed, the next-generation products can easily be made to include PCIe, USB 3.0, 10/100/1Gbyte and other performance enhancing blocks like 550 MHz ARM 9 core, Digital Content Management, etc.

MosChip has developed a number of domain solutions (storage, consumer, IPC and others) with FEP using its Network Appliance Processor SoC. Interoperable functional blocks that include Ethernet, USB, PCIe, ISA, GPIO, among others, are designed and are readily available. This makes for an ecosystem that has a myriad of design options, allowing the quick swap out of functional blocks to create new high-performance designs in rapid time.

Connectivity Needs More SoC and FEP Support

The next-generation PCIe, USB or Ethernet interfaces will introduce additional integration challenges with high-speed interfaces that may call for a switch between the current versions of interfaces. Issues that might make a difference are as follows:

I. Possible Differentiating Factors over Current Connectivity:

• Data transfer rates more than 10 to 20 times faster

• Optimized for low power

• Improved protocol efficiency

• Ports and cabling will be designed with both copper and optical cable

II. Possible Architectural Issues:

• Higher CPU usage

• High-speed connectivity link will require separate connector

• Dual connectivity (high speed and low speed) links be available one at a time

In scenarios where you will be switching between current and next-generation technologies, FEP becomes very ideal at enabling designs to address both. This is especially true for popular connectivity technologies such as USB, PCIe or Ethernet where the last thing you want in a system is a connectivity bottleneck.

In addition, USB links can be expanded using StackableUSB technology (www.stackableusb.org). Using this technology, I/O cards can support up to 16 StackableUSB boards. This technology is suitable for Industrial and Embedded USB applications. It uses the established PC/104 and PC/104-Plus stacking architectures and allows an automatic link with all connected devices with minimum human intervention. In an SoC architectural implementation, the USB port links for all sixteen boards and routing links need to be implemented.

The use of the FEP concept can facilitate having a comprehensive suite of connectivity solutions within a one-time design effort that can address multiple vertical segments from current-generation to next-generation products such as USB 3.0. This approach can greatly speed your design times to more effectively, efficiently and economically meet legacy and next-generation connectivity market needs with a faster time-to-market.

MosChip Semiconductor
Irvine, CA.
(949) 276-9750.
[www.moschip.com].