RTC Magazine

The connectivity needs of industrial, automotive and consumer computing continue to grow to encompass everything from USB to PCI Express (PCIe). Unlike component-level solutions, System-on-a-Chip (SoC) technology has the ability to integrate multiple connectivity solutions on a single silicon chip, cutting development cycles and costs while increasing product functionality, performance and quality. As a result, embedded designers are more often integrating connectivity and high-performance processor IP on the same SoC. However, this connectivity integration has to be universally accepted, processor agnostic and have the ability to remove bottleneck constraints. Emerging next-generation standards, such as PCIe Gen2, add to functionality, performance and quality demands. As such, embedded designers face great challenges in balancing integration of appropriate connectivity blocks while maximizing performance for highly competitive consumer, industrial, automotive and other verticals.

Among all options, USB is probably the most versatile and successful connectivity standard in computing history, in regards to addressing multiple vertical segments. It has been implemented in PCs, peripherals, digital imaging, audio, video, wireless and wired networking, storage, automotive, industrial, home-automation, mobile phones and more.

Franchising a Platform for Connectivity

It stands to reason that with so many connectivity variables available in a product design, perhaps “franchising” a platform where only small changes are needed to implement such varieties might be ideal. The key concept behind franchising an embedded platform–dubbed Franchisable Embedded Platform (FEP)–is the ability for integration that addresses multiple verticals within a single SoC. Consider FEP as a one-time investment, from the viewpoint of an ASIC and a system, in capturing specific vertical segments with your brand. With FEP, you can quickly enable the repurposing of existing designs to suit new connectivity needs. FEP will help designers meet the latest connectivity requirements and turn around new designs within a limited marketing window. FEP can also aid in meeting price targets and maintaining system performance and compatibility with industry standards.

The concept is especially effective as it relates to marrying various connectivity options on a SoC to better meet integration challenges. For example, if we pick a popular connectivity standard like USB to start with, we can connect with almost all key market segments (PC, consumer, industrial, etc.). Now, if we keep adding other connectivity blocks one at a time, we can more specifically target a market segment. In this conceptual way we can attain a true franchisable embedded silicon platform to meet multiple market segments, because with an incremental change in system design, we can have a number of systems to suit a number of markets.

FEP can greatly optimize the process of spinning new SoCs for every vertical. All four major stages of designing an SoC–specifications, integration, verification and implementation–are virtually eliminated.

Designing Connectivity with FEP

The base design must be done with multiple considerations in mind: appropriate market research and trade-offs for every vertical segment, their required performance turnaround time, a review of the overall benefit of the integration, and target cost. Selective integration of functional blocks is the key to creating the SoC that can address differing vertical segments with incremental design modifications at the FEP level. For example, if you created a system with Ethernet to PCIe, and you later come to realize a new market requirement for Ethernet to USB, FEP makes it possible to reconfigure the existing device with EPROM and a few physical connectivity changes to quickly arrive at a new design.

Another key consideration while dealing with connectivity is the protocol standards. These include the implementation of the logical link layer, MAC layer and physical layer. Now, the goal is to get the best possible design from the integration of multiple connectivity options using multiple standards on a single platform. Implementing this at the board level defeats the purpose of FEP, and so a wiser choice is to implement them on one single die so that options like USB, Ethernet, PCI, PCIe, ISA, GPIO, etc. are on one single die (Figure 1). Such SoC connectivity can be stand-alone or put together around an embedded processor, such as an ARM 9. Having all these pieces on single die will eliminate most delay issues, enhance signal integrity, add data crossover security, improve design-in time, add design stability and will address many other marketing and business-related issues (Figure 2).