With the advances in FPGA technology and hardware standards, COTS vendors are developing FPGA-based products in increasing numbers, providing developers with an unparalleled selection of platforms to build their systems.


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FPGAs are rapidly becoming ubiquitous for signal processing functions in a number of application areas. COTS vendors have responded to this trend by developing an array of products that address the needs of a variety of applications in the defense world and beyond. In many cases, these COTS products are developed using popular industry standards, thus allowing developers to establish a base platform that can address a wide range of applications.

At a card level, VME has long been established as a widely used platform in embedded systems. Competitors have come and gone, but an unparalleled depth of installed base and an evolutionary approach to new technology has seen VME adapt to meet ever changing requirements. The development of VXS (VITA 41) heralded the arrival of a range of serial fabrics to VME platforms, but not, critically, at the loss of support for legacy products and systems. VPX may represent the future of VME systems, but the pace of change will be dictated by the market, and indications so far have been that many developers value the backward compatibility of VXS too much to switch (no pun intended) to the “serial-only” backplanes of VPX. Some highly complex applications have been compelled to make use of the added bandwidth of VPX, but it appears that VXS may be around for longer than many originally suspected.

VXS specifies two 4X lanes offering a total bandwidth of 20 Gbits/s carried over the P0 connector. Backplanes are available in mesh, star and dual-star topologies, but one of the challenges of VXS is deciding which specific serial standard to use. VITA 41 has 11 “‘dot” standards, with 7 dedicated to supporting serial protocols such as InfiniBand, Serial RapidIO, Gigabit Ethernet and PCI Express (Table 1). In embedded applications, where distributed multiprocessing architectures are common, Serial RapidIO has emerged as a popular choice due to its support for peer-to-peer communications and performance-optimized data transfers.

In the same way that VXS added serial capability to VME, XMC (VITA 42) represents an evolutionary introduction of serial fabrics to the PMC mezzanine standard. The XMC standard defines two high-speed serial connectors that can be used in addition to the four PMC connectors (to create a “hybrid PMC/XMC”) or in isolation (to create a “pure XMC”). In either case, a total of 20 differential pairs are available on each connector, but they are usually configured to provide 8 bi-directional serial lanes on each connector for a total bandwidth of 40 Gbits/s. As with VXS, XMC has dot standards for the usual range of serial protocols.

FPGA Architectures

This extra bandwidth on VME and PMC products has made the use of FPGAs—and their parallel processing capability—a far more viable proposition; a fact reflected in the plethora of standards-based COTS FPGA products that are now available. Developers can select from a range of carrier architectures to provide a powerful and flexible base architecture that can be customized to meet the needs of a range of applications.

The VXS-610 is an example of an FPGA and PPC compute card with dual FPGA processing nodes, a PowerPC and two PMC/XMC mezzanine sites. It has an onboard Serial Rapid IO switch that provides an intelligent, high-bandwidth network for building multicard compute systems. The PMC/XMC hybrid sites provide two interfaces to the mezzanines—a PCI-X bus and 8 lanes of serial I/O. The PCI-X bus provides communication with the onboard PowerPC and the PCI-to-VMEbus bridge. The 8-lane XMC interface from each mezzanine site is connected directly to a Virtex-5 FPGA on the carrier card, providing a high-bandwidth data plane for moving data off or onto the mezzanine.

Selecting a common base architecture allows for a great amount of re-use at the architectural level. In this case, systems developers can create software management routines that set up and control the Serial RapidIO network and can be easily altered depending on particular data-flows and without restricting the selection of the two parameters that vary most from one application to the next—the I/O interface and the processing requirements.

Varying I/O

Variations in I/O requirements are one of the reasons modular standards were developed in the first place. Two SIGINT applications may only differ in the frequency spectrum of interest, but this still imposes completely different I/O requirements on the hardware platform.

As an example, radar systems need to operate at UHF and upwards (300 MHz - 3 GHz), requiring digitizing capabilities of greater than 1-3 Gsamples/s, while a COMINT system will be interested in VHF signals (30-300 MHz) but will require greater fidelity in order to distinguish carrier signals.

An XMC card provides two 3 Gsample/s, 8-bit ADC channels fed into a Xilinx Virtex-5 FPGA, making it appropriate for several applications including radar and lidar systems and mobile communications. Two of these PMC/XMCs can be mounted on the VXS board providing four independent sensor inputs—ideal for antenna arrays. The ability to digitize the sensor data at these RF frequencies removes the need for an intermediate frequency (IF) stage and consequently some complex analog circuitry, but does lead to a combined data rate for the two channels of 6 Gbytes/s (48 Gbits/s). This places a requirement on the FPGA to have massive I/O bandwidth and enough processing power to decimate the incoming data streams. Fortunately, FPGA technology has advanced significantly in recent years, outstripping conventional processors hampered by the slowdown in Moore’s law. This has made FPGAs the first choice for front-end sensor processing applications for the very reason that they can handle the data rates that exist at this stage of the system.

The 3 Gsample/s ADCs have built-in 1:4 multiplexers plus the ability to use double-data rate (DDR) registers, meaning that data emerges from each ADC on 32 LVDS pairs running at 375 MHz (DDR). This translates to a data rate on each LVDS pair of 750 Mbits/s. To ease the difficulty of receiving such high-bandwidth data, the Virtex-4 and Virtex-5 families of FPGAs from Xilinx offer SelectIO technology, which provides support for over 40 I/O standards and has dedicated logic blocks with DDR registers and built-in serial-to-parallel converter units, called “ISERDES”. In DDR mode, the ISERDES blocks convert incoming serial data lines into 4-, 6-, 8- or 10-bit parallel words, relaxing the clock frequency requirements on the FPGA fabric. In this specific example, a 4-bit word helps to reduce the clock frequency by another factor of 2—to 187.5 MHz. The data flow from ADC through to FPGA fabric is illustrated in Figure 2.

The ISERDES blocks are extremely valuable when dealing with high-speed I/O, but while they help to get the data into the FPGA, they do not change the volume of data that must be processed. When dealing with such a large amount of data, the first processing functions focus on reducing the data-stream into something more manageable that can be analyzed. The typical functions are included in Figure 2.

The digital downconversion (DDC) process shifts the channel of interest to a lower carrier frequency, filters unwanted signals using a finite impulse response (FIR) filter and reduces the remaining data to a more manageable rate. The DDC does not consume a large amount of FPGA resources, requiring around 40-50 DSP48 blocks in the Virtex-5, assuming a 40-tap FIR filter is used. Even when dealing with multiple channels, today’s FPGAs have ample space left to process the data through, say a 4k-point FFT. This means that when the data leaves the XMC it has already been pre-processed such that the next stage of processing is focused on analyzing the data and making decisions.

For COMINT applications, the XMC-220 card provides dual 180 Msample/s, 16-bit ADC channels and can be mounted on the VXS board in the same fashion as the XMC-210. This means that the software infrastructure built up around the radar application can be adapted and re-used as appropriate. The XMC-220 also has dual 1 Gsample/s, 16-bit DAC channels, which can be used for generation of jamming signals or as test stimulus during application development.

Beyond defense and SIGINT systems, a wide range of PMC/XMC products exist providing every kind of I/O imaginable. 10Gbit Ethernet products are now available, allowing development of more advanced packet snooping systems targeted at monitoring the explosion of data on the Internet. The base architecture of the VXS example supports this class of product with FPGA processing nodes that enable real-time processing of huge volumes of data in a “kink in the wire” configuration.

Processing Requirements

Xilinx currently offers four families of devices in its Virtex-5 product range, each offering an optimized balance of features for particular applications. The LX and LXT series offer the best logic performance while the SXT family is optimized for signal processing and memory-intensive applications. The recently announced Virtex-5 FXT series provides a balanced set of logic and signal processing features as well as embedded PowerPC blocks. All of the “T” products incorporate RocketIO GTP transceivers—dedicated silicon blocks that implement a range of high-speed serial I/O protocols.

As with most signal processing applications, the Radar and COMINT applications described previously are best served by the SX95T device, which has 640 DSP-48 slices permitting 640 multiply-accumulate functions (MACs) on each clock cycle.

Applications such as packet snooping tend to perform more logical, conditional processing that requires bit-level manipulation rather than floating-point numbers, making the superior logic count of the LX devices a perfect fit.

The VXS-610, XMC-210 and XMC-220 provide the option of SXT or LXT devices, allowing users to select a platform that is optimized to meet the requirements of their particular application. Table 2 illustrates the relative features of the specific devices.

The interoperability of such an array of products is extending the flexibility of FPGAs to a system level, enabling them to address a growing range of applications from FPGA staples such as SIGINT and Software Defined Radio to packet snooping and protein matching. Using a common hardware base for multiple applications also facilitates software re-use, reducing schedule and risk in an increasingly competitive embedded market. This expansion in COTS FPGA products may also have an interesting effect on the roadmaps of the large FPGA vendors who have traditionally focused more on replacing ASICs.


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