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InterphaseTECHNOLOGY IN CONTEXT
FPGA-BASED BOARD SOLUTIONS
FPGA-BASED BOARD SOLUTIONS: One Platform, Many Apps
With the advances in FPGA technology and hardware standards, COTS vendors are developing FPGA-based products in increasing numbers, providing developers with an unparalleled selection of platforms to build their systems.
NEIL HAROLD, NALLATECH
FPGAs are rapidly becoming ubiquitous for signal processing functions in a number of application areas. COTS vendors have responded to this trend by developing an array of products that address the needs of a variety of applications in the defense world and beyond. In many cases, these COTS products are developed using popular industry standards, thus allowing developers to establish a base platform that can address a wide range of applications.
At a card level, VME has long been established as a widely used platform in embedded systems. Competitors have come and gone, but an unparalleled depth of installed base and an evolutionary approach to new technology has seen VME adapt to meet ever changing requirements. The development of VXS (VITA 41) heralded the arrival of a range of serial fabrics to VME platforms, but not, critically, at the loss of support for legacy products and systems. VPX may represent the future of VME systems, but the pace of change will be dictated by the market, and indications so far have been that many developers value the backward compatibility of VXS too much to switch (no pun intended) to the “serial-only” backplanes of VPX. Some highly complex applications have been compelled to make use of the added bandwidth of VPX, but it appears that VXS may be around for longer than many originally suspected.
VXS specifies two 4X lanes offering a total bandwidth of 20 Gbits/s carried over the P0 connector. Backplanes are available in mesh, star and dual-star topologies, but one of the challenges of VXS is deciding which specific serial standard to use. VITA 41 has 11 “‘dot” standards, with 7 dedicated to supporting serial protocols such as InfiniBand, Serial RapidIO, Gigabit Ethernet and PCI Express (Table 1). In embedded applications, where distributed multiprocessing architectures are common, Serial RapidIO has emerged as a popular choice due to its support for peer-to-peer communications and performance-optimized data transfers.
In the same way that VXS added serial capability to VME, XMC (VITA 42) represents an evolutionary introduction of serial fabrics to the PMC mezzanine standard. The XMC standard defines two high-speed serial connectors that can be used in addition to the four PMC connectors (to create a “hybrid PMC/XMC”) or in isolation (to create a “pure XMC”). In either case, a total of 20 differential pairs are available on each connector, but they are usually configured to provide 8 bi-directional serial lanes on each connector for a total bandwidth of 40 Gbits/s. As with VXS, XMC has dot standards for the usual range of serial protocols.
FPGA Architectures
This extra bandwidth on VME and PMC products has made the use of FPGAs—and their parallel processing capability—a far more viable proposition; a fact reflected in the plethora of standards-based COTS FPGA products that are now available. Developers can select from a range of carrier architectures to provide a powerful and flexible base architecture that can be customized to meet the needs of a range of applications.
The VXS-610 is an example of an FPGA and PPC compute card with dual FPGA processing nodes, a PowerPC and two PMC/XMC mezzanine sites. It has an onboard Serial Rapid IO switch that provides an intelligent, high-bandwidth network for building multicard compute systems. The PMC/XMC hybrid sites provide two interfaces to the mezzanines—a PCI-X bus and 8 lanes of serial I/O. The PCI-X bus provides communication with the onboard PowerPC and the PCI-to-VMEbus bridge. The 8-lane XMC interface from each mezzanine site is connected directly to a Virtex-5 FPGA on the carrier card, providing a high-bandwidth data plane for moving data off or onto the mezzanine.
Selecting a common base architecture allows for a great amount of re-use at the architectural level. In this case, systems developers can create software management routines that set up and control the Serial RapidIO network and can be easily altered depending on particular data-flows and without restricting the selection of the two parameters that vary most from one application to the next—the I/O interface and the processing requirements.