Small Form Factors put the Squeeze on Chip Vendors


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Welcome to the first edition of Small Form Factor Forum (SF3). SF3 will appear monthly to share ideas and observations of interest to the small form factor board community and highlight new products and technologies in the ecosystem that will feed the growth of this hot market area. We welcome your feedback and suggestions for future topics at

Today, we highlight the obvious—or at least you would think so. As SBC and COM (Computer-on-Module) form factors shrink to a footprint about the size of a business card, it becomes incredibly difficult to fit today’s off-the-shelf processors and chipsets onto these boards.

It wasn’t that long ago that the industry was at a loss on how to fit a Pentium M solution on a PC/104 board. PC/104 allows a surface area of about 70 mm on a side for placing components after connector zones are excluded. But with a Pentium III or Pentium M or Core Duo solution consisting of three chips (CPU, Northbridge, Southbridge) each 35 mm on a side, along with 500-1000 other components, it’s pretty plain to see that you can’t build one of these boards without coming face to face with dozens of design rules for reliable manufacturing, such as spacing between components.

Even more disastrous are the resulting buried and blind vias, making testing a nightmare and rework impossible. The industry made it work by fudging on the form factor, adding PCB space in the area the PC/104 standard calls out for I/O connector overhang (or “wings” in the industry vernacular). With a little wink-wink, we can all agree that this meets the letter, if not the spirit of the standard. But now we have new boards, primarily in the COM space, that make the PC/104 form factor look gigantic.

There’s good news and bad news here. While x86 chip vendors appear highly reluctant to market chips designed specifically for the embedded market (we’re too small and diverse for the enormous design investment required), Intel and VIA have decided to focus on a new sub-notebook market dubbed the Ultra Mobile PC (UMPC). The good news is that these handheld devices have many of the same power, size and performance requirements as the SFF embedded market and have driven the chip vendors to integrate chips and shrink packages.

VIA has been marketing a Northbridge-Southbridge combo chip for two years and has shrunk this package from 35x35 mm to 21 x 21 mm. VIA has also shrunk the CPU package from 35x35 mm to 21x21 mm and new designs will take this to 11x11 mm. Intel offers multiple solutions including one headless offering for network appliances that combines CPU, Northbridge and Southbridge into a single SoC. And Intel’s new Atom processor for UMPC shrinks the CPU package to 14x13 mm while combining North and Southbridge into a single 22x22 mm chip.

All good. The bad news is that few people anticipate a UMPC device needing bus expansion or legacy I/O. Luckily, VIA has done a better job so far, based on announced products, in providing a bridge from the past by including support for external legacy I/O chips and a PCI bus at a cost, some would argue, of lower overall system performance. The mainstream 80% of embedded applications benefit from this trade-off.

So what we’ve found in the SFF space is that size matters. And the chip guys are starting to get it, finally. But size isn’t everything. There’s the other little matter called heat dissipation. When you have a PCB that’s 50 mm square or smaller with 600 or 700 components on it, getting the heat out of that environment is a major problem.

Fortunately the UMPC market has the same heat removal issue. Hence, as the chip packages get smaller and die size shrinks, the Thermal Design Power (TDP) ratings have dropped as well, particularly for processors under 1.0 GHz. The 1W TDP processor at 500 MHz is a reality for these new designs. But another problem crops up. In many designs now, the heat from the chipset (single chip or two chips) exceeds the heat generated by the processor. When we had 20W processors, a 4W chipset wasn’t really a concern. With a 1W processor, the 4W chipset looks like a big pink elephant.

So maybe the answer for the small form factor community is that which has been in front of us all along—moving from x86 designs to highly integrated, ultra-low-power SoC devices using RISC cores. After all, it’s just a SMOS (small matter of software). But, alas, there is more here than meets the eye, so that is the subject for another column.