CompactPCI Express Comes of Age
CompactPCI Express is an excellent complement and enhancement to the world of PCI standards. It is now possible to use hybrid backplanes to cost-effectively upgrade systems. The standard could still benefit from some enhancements with additional I/O standards.
STEPHEN CUNHA, MEN MICRO
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In the two years since CompactPCI Express (CPCIe) was formally adopted as a standard by PICMG, several companies in the industrial, transportation, medical, and test and measurement industries, to name a few, have begun to incorporate this new technology into a variety of embedded computing systems.
CPCIe enables increased bus performance as well as enhanced data transfer rates and throughput for applications that have traditionally used a PCI or 3U CompactPCI (CPCI) bus, making it suitable for applications requiring complex communication, powerful visualization and digital and analog signal processing. Such improved performance is also particularly attractive for high-volume data transfer requirements, as found in data-intensive computing, Gigabit Ethernet or graphics applications.
The significant advantage of the CPCIe bus, as compared to the older CPCI bus approach, is that it uses full-duplex, point-to-point, high-speed serial link connections—each comprising one or more “lanes”—instead of forcing all data through a common parallel bus connection. This scalable, packet-based architecture allows multiple bus participants to transfer data concurrently at full speed (250 Mbytes/s for each lane). The net result is the ability to handle higher data volumes—the equivalent of 2 Gbytes/s for an 8-lane link and 4 Gbytes/s for a 16-lane link.
If a designer is constructing a new system around CPCIe, there will be virtually no issues with backward compatibility, since all components will be up to the standard’s specifications. However, not all applications require brand new systems. And, if careful consideration is not taken, the costs associated with implementing CPCIe within existing systems can be exponential since the designer needs to work around existing technologies and components while ensuring that the upgrades provide the best incorporation of existing technologies.
Cost-Effectively Including CompactPCI Express
Fortunately for current CPCI users, the new CPCIe interface is compatible with all software utilized in existing CPCI applications. But there are multiple hardware configuration considerations for CPCI users seeking to enhance existing applications with faster speeds and increased throughput made possible by the CompactPCI Express format—each with its own capabilities and costs.
Starting from scratch and instituting a “pure” CPCIe solution will enable you take advantage of higher CPCIe transmission speeds for all peripheral card slots, but requires all new—and typically more expensive—CPCIe peripheral card and backplane hardware. This approach could be cost-effective for new applications, yet less so for partial upgrades of legacy applications that can still utilize existing CPCI cards for some of their functions.
One approach to legacy systems is to install a bridge that receives the CompactPCI Express signal from the systems slot and converts it to CompactPCI but will require you to sacrifice a slot on the backplane to hold a bridge board supporting the active logic to convert the signals. Using a bridge at the rear of the system avoids the necessity of sacrificing a slot in the backplane, but requires the use of a bridge clip that adds cost for duplicating functionality already existing in the latest chip sets, such as the Intel 945 and 965.
Another alternative is to adopt a hybrid backplane solution. Incorporating both CPCI and CPCIe capabilities in one board provides a cost-efficient migration path for upgrading to CPCIe performance in areas where it is needed most, without having to scrap or modify legacy CPCI peripheral card applications that still function acceptably through a CPCI bus.
Hybrid Technology Eases Migration
This hybrid system approach has provided a cost-effective way for companies currently employing CPCI to take advantage of the enhanced CPCIe capabilities. Through components that enable both CPCI and CPCIe to function in the same system, engineers can cost-effectively utilize the technologies built on this new standard to reduce component obsolescence, incorporate technological refreshes into existing designs, and provide a simple migration from CPCI to CPCIe. These blended systems preserve compatibility with existing CPCI systems while at the same time providing the high serial data rates of CPCIe, so users can achieve the rugged requirements necessary for their specific applications at a reasonable cost.
For example, MEN Micro and Schroff have collaborated to develop a CPCI/CPCIe system that partners a Schroff backplane with MEN Micro’s scalable Intel product family, a CompactPCI Express extension board and an XMC carrier board to provide flexible system configurations. This hybrid configuration also eliminates the need for software re-writes and expensive new software for serial link connections, and helps save costs by enabling the Express function to be used only where high data rates are required, such as in high-end graphics and Ethernet functions (Figure 1).
With CompactPCI on one side and CompactPCI Express on the other, a smooth migration path from parallel to serial is provided and the 3U form-factor is maintained. Expensive bridge boards with active logic, which waste space on the system, and bridge chips on the backplane that reduce speed because of multiple bridges in the system, are unnecessary. In addition, with a hybrid solution, future applications will not need to have a high-speed serial connection to devices like the typical industrial I/O, so it is pointless to buy pricey backplanes and connectors.
Figure 2 shows an 8-slot hybrid backplane with no bridge or active logic that allows four slots for CPCI cards and four for CPCIe cards. The CPCI slots are arranged with 32-bit CompactPCI bus and rear I/O on P2. The CPCIe slots include the CompactPCI Express system slot arranged as a 4-link configuration connected to three type-2 peripheral slots, each with a x4 link. An additional x4 link directed to the slot situated at the farthest right position also makes a x8 link configuration possible from that slot. Both the CPCI and the CPCIe buses are accessed from one CPU board.
Commercially available hybrid backplanes that provide such dual capability transparently—at costs comparable to those of standard CPCI backplanes—enable you to maintain an existing 3U form-factor and existing CPCI peripheral cards where desired, so you can concentrate your investment in CPCIe components needed only for more demanding applications.
Room for Improvement
Although CompactPCI Express offers significant cost-saving and technology upgrade benefits, a few simple enhancements to the data storage and transfer functions would provide exponentially increased opportunities for CPCIe and would help to further the adoption of this standard within several industries.
With the performance advantages that it provides to embedded computing, multiprocessing will remain a sought-after feature for many generations of systems and subsystems. Multiprocessing functions are intensifying, resulting in significant increases in data capture, sharing and transfer requirements. Gigabit Ethernet, the widely used networking technology, could be incorporated via the backplane’s I/O to provide exponentially more multiprocessing capabilities.
Currently used in common applications, such as game controllers, printers, scanners, digital cameras, MP3 players, hard disks and flash drives, wireless USB (WUSB) is a wireless adaptation of the industry-standard USB protocol, which is currently used in more than two billion connection arrangements. A simple WUSB interface incorporated into the CPCIe standard would provide high-bandwidth wireless connectivity with high data transfer rates, providing more flexibility, ease-of-use and mobility.
A SATA interface would also provide faster, more reliable data transfers, with CRC (cyclic redundancy check) error checking on all data and control information, and hot swap capabilities for connecting 2.5” hard disk drives. SATA on the backplane would enable the user to accomplish data storage subsystems, including RAID expansion, on a much higher level.
New and improved standards claiming to be the next best thing for embedded computing applications have been popping up in an almost alarming number over the past few years. However, the standards that will bring true benefit to the market are those that exhibit a sound roadmap for future usage, offer cost-effective migration within existing systems and provide significant performance advancements. With a little forethought and enhancement, CompactPCI Express could easily be one of the standouts that will help developers realize the best return on their investment. It has shown great progress over the past few years, and it is poised to become a critical standard in the embedded community.