TECHNOLOGY IN CONTEXT
Mezzanines in communication
Mezzanine Board Strategies for Communications
Mezzanines offer an excellent solution to local high-performance signal acquisition and preprocessing, saving costly processor resources. With FPGAs, they can be reconfigured to meet new communications standards extending system life cycle.
RODGER H. HOSKING, PENTEK
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Few embedded system applications encompass a more diverse range of signal frequencies, signaling schemes, numbers of channels, data rates and signal processing algorithms than communications systems. Apart from this extreme diversity, communications systems must now handle wider signal bandwidths to meet the needs of new complex modulation schemes and higher data rates to support large numbers of these channels.
System integrators faced with the task of delivering custom communication systems using COTS board-level products have traditionally relied on mezzanine boards (or daughter cards) for modular and flexible interfaces.
But new technologies and new mezzanine standards have cast mezzanines for communication systems into complex and critical roles previously handled by other full-size boards in the system. By cutting costs and boosting performance, choosing the right mezzanine boards now becomes a much more significant part of successful system design.
Communication System Basics
The receiver section of a modern communication system typically starts with an analog RF stage that amplifies and down-converts the antenna signal to an intermediate frequency (IF), as shown in Figure 1. This IF signal can then be digitized by a wide range of monolithic A/D converters capable of 14- or 16-bit accuracy and sampling rates of 100 MHz and higher. The IF signal bandwidth usually covers the entire span of the particular communication band and may contain many different carriers, each at its own frequency.
Extracting multiple signal channels from this digitized IF band requires digital down-conversion (DDC). This process starts with a digital local oscillator that produces samples of a sine wave set to the carrier frequency. The samples from the A/D are then mixed with the oscillator samples using a digital multiplier. This translates the carrier signal down to baseband and produces a complex (I+Q) digital signal with upper and lower sidebands centered at 0 Hz. A digital low pass filter set for the signal bandwidth removes adjacent channel signals, leaving only the channel of interest. Because the bandwidth of the filtered output has been reduced, an output decimator drops the sampling rate commensurate with that bandwidth.
Finally, depending on the type of transmission, additional processing steps for demodulation, decoding and decryption are needed to recover the receive channel data. All of the digital signal processing steps shown in the top half of Figure 1 to the right of the A/D must be repeated for each channel.
On the transmit side, the signal processing steps are exactly reversed, as shown in the lower half of Figure 1. Transmit channel data must first be processed with the appropriate modulation, encoding and encryption to make it compatible for the transmission channel protocols. The digital up-conversion (DUC) stage then follows. Here, the digital sample stream signal enters an interpolation filter, which preserves the frequency characteristics of the signal, but boosts the sampling rate to match the sample rate of the digital mixer and local oscillator. These stages up-convert the baseband transmit signal to the IF frequency. A D/A converter produces an analog IF signal, which is fed into the analog RF transmitter section to drive the antenna. All of the signal processing steps to the left of the D/A must be repeated for each channel.
Because the A/D and D/A converters generate and require sampled data streams at very high sample rates, general-purpose programmable processors cannot reasonably handle these substantial DSP tasks. Instead, designers often choose ASICs targeted for the specific receive and transmit requirements of the signal channel. However, because of the variety of communication signal types and frequency characteristics, the signal processing tasks tend to be quite unique for each system. As a result, there is no single standard ASIC available to handle a wide range of applications.
Emerging Mezzanine Standards
Successful adoption of mezzanines springs directly from standardization of mezzanine architectures. Standards create win-win situations by assuring customers of multi-vendor availability and competitive prices, and assuring board vendors of a viable marketplace worthy of investment in product development. Several popular mezzanine standards emerging during the last few years have hit home runs. Topping the list is the ubiquitous PCI Mezzanine Card (PMC) and its unfolding series of performance enhancements.
A new standard that defines gigabit serial links to mezzanine boards for embedded communication systems is defined in the VITA 42 standard, also known as XMC. As an extension to PMC, the XMC specification defines two new connectors that join the mezzanine board to the host or carrier board. At serial bit rates of 3.125 GHz, a dual connector XMC interface supports data rates of 5 Gbytes/s in each direction.
Although not yet fully adopted, various draft sub-specifications for VITA 42 shown in Table 1 define the implementation of industry standard switched fabrics. Popular serial fabric clock rates, the number of data lines and the resulting transfer rates in each direction are shown for either one (J15) or two (J15 and J16) XMC connectors.
FPGAs on Communication Mezzanines
Among the first products to take advantage of FPGA technology are mezzanine boards. Because of this, as the features and densities of new FPGA families emerged, they significantly impacted the architectures of communication systems in many different ways. Not only can FPGAs be configured to implement numerous electrical interface standards, they can also implement a variety of communication algorithms for modulation and demodulation, encoding and decoding, encryption and decryption along with protocol handling.
By offloading these real-time DSP, logic and bit-rate processing tasks from general-purpose programmable DSP or RISC processors, fewer processor boards are needed in the system, saving significant costs. Further, these front-end FPGA engines can extract signal information before it leaves the mezzanine module, resulting in less downstream traffic and lower system data rates.
Since FPGAs can be reconfigured to perform new functions without having to redesign the mezzanine PC board, they can accommodate new communications standards and protocols to help safeguard against product obsolescence, both at the board level and at the deployed system level. When upgrading older communication systems, a single FPGA-based product can replace several legacy products, thanks to improved logic density and flexible interfaces.
As if these benefits were not enough, FPGAs are the primary enabling technology for the new XMC gigabit serial extensions to PMC modules. During the last few years, FPGA emerged from Xilinx featuring gigabit transceivers called RocketIO MGTs (multi-gigabit transceivers), while Altera offers counterparts dubbed Stratix-GX MGTs. Data channel encoders and decoders support these physical interface drivers and include serial/parallel conversion so that data and clock are combined in the signaling on each differential pair over the external serial channel. Serializer/deserializer (SERDES) blocks, built right into the FPGA, include circuitry for both receive and transmit functions.
A protocol engine within the FPGA interfaces with the SERDES to correctly process packets, header information, control functions, error detection and correction and payload data format. Since each switched serial fabric standard has its own protocols and rules, FPGAs offer excellent flexibility by allowing users to install the appropriate IP core protocol engine. The strategy makes FPGA-based XMC modules truly “fabric agnostic” and allows one hardware design to be deployed in several different fabric environments.
Enhanced Digital Up- and Down-Conversion
By taking advantage of FPGA technology to extend the bandwidth range of the ASIC devices, commercial off-the-shelf mezzanine modules for communication systems can become flexible enough to satisfy a wider range of markets and signal types.
Figure 2 shows a typical software radio transceiver PMC/XMC mezzanine module for communication systems. It features two 14-bit 105 MHz A/Ds and two 16-bit 500 MHz D/As connected to a Xilinx XC2VP50 FPGA. Two ASIC devices handle DDC and DUC functions with memory, timing and system interfaces completing the product. Note that the XMC interface uses the built-in RocketIO gigabit serial transceivers of the FPGA.
The DDC ASIC is a Texas Instruments GC4016 four-channel narrowband device with decimation settings ranging from 32 to 16,384. Since channel bandwidth is inversely proportional to the decimation factor, a factor of 32 limits the maximum channel bandwidth to about 2.5 MHz, falling far short of many communication signal types.
To handle wider signals, two wideband DDC IP cores are installed in the FPGA with decimation settings ranging from 2 to 64, delivering a maximum channel bandwidth of 40 MHz for both A/Ds. Programmable data switches inside the FPGA allow the wideband DDC cores to be driven directly from the A/D converter or in cascade from the outputs of the GC4016 DDC. This extends the maximum decimation of the GC4016 by a factor of 64. By including the new wideband DDC core, the overall decimation range for the mezzanine now becomes 2 to 1,048,576 instead of the previous 32 to 16,384. This extended range translates directly to an enormous range of input signal bandwidths from 76 Hz to 40 MHz.
The DUC ASIC is a Texas Instruments DAC5686 wideband device with interpolation settings of 2 to 16. Like the DDC, the output channel bandwidth is inversely proportional to the interpolation factor, so with a maximum interpolation setting of only 16, narrowband transmit signals are not supported. To handle narrowband signals an interpolation filter is installed in the FPGA with programmable interpolation factors from 16 to 1024. Again, a programmable data switch allows the ASIC DUC to be driven directly from the data interface for wideband signals or from the output of the interpolation filter for narrowband signals. With the interpolation core, the overall interpolation range extends from 2 to 16,384 instead of the previous 2 to 16. It can now accommodate output signal bandwidths from 4.8 kHz to 40 MHz.
Since all of these critical functions fit in a such a compact form-factor as shown in Figure 3, it is easy to see why FPGAs have been so widely deployed on mezzanine modules for communication systems. Of course, many other signal processing tasks such as those shown in the transmit and receive signal processing blocks in Figure 1 can also be handled by the FPGA.
More sophisticated signal processing operations such as beamforming techniques can lead to significant improvements in communication systems. Examples abound along the highway where numerous cell phone towers show arrays of vertical antennas, usually in groups of four. Signals from multiple receive antennas can be phase shifted by using the mezzanine module memories as digital delay blocks to enhance reception of a signal arriving from a specific direction. Likewise, transmission using multiple antennas with phase-shifted signals can steer the outgoing signal toward a specific target. This not only provides better service to subscribers but also allows frequency reuse within a cell by dividing the cell into beam-formed pie-shaped sectors.
When new critical ASIC devices emerge, the standardization and modularity of mezzanines support new technology insertion by simple replacement, rather than scrapping a whole system. This modularity also reduces maintenance, troubleshooting and service costs. And finally, the switched fabric interfaces already available on many mezzanine modules ensure plenty of data bandwidth for future wideband signal types.
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