I/O and Sensor Technology

From FPDP to VPX: Back-End Management and Processing of Sensor-Derived Data

From custom-built to COTS-based solutions, rapidly evolving technology is transforming the way sensor-captured data is managed and processed–notably due to the advent of serial switched fabrics and FPGA technology.


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System design is all about the art of the possible. After the governments of the USA and other countries mandated the use of COTS in the early 1990s, one of the first tasks was to develop VME-based COTS components suitable for upgrading large sonar systems on existing naval vessels. The requirements of such systems are complex because they generally involve a large number of analog channels, high sample rates, complex interfacing and data formatting, large computing power for beam forming, filtering and demodulation and a high data transfer rate.

Data flow management was a significant challenge in early COTS systems due to the extremely limited bandwidth of the VME backplane. To overcome this barrier, a number of VME board vendors—led by ICS Sensor Processing, now part of GE Fanuc Embedded Systems—pioneered a unidirectional data flow architecture called the Front Panel Data Port, or FPDP. This is a 32-bit synchronous port that, in its initial version, offered a sustained throughput of 160 Mbytes/s. It is busable with multi-drop capability so that blocks of data can be either added to, or extracted from, a frame of FPDP data on a timeslot basis. Connection to the port is made via an 80-way ribbon cable connector located on the front panel of each board.

Dedicated DSP devices were the optimum choice for sonar signal processing since they easily outperformed the general-purpose processors of that era. By optimizing the DSP board architecture for sonar operations (such as FIR filtering/decimation, complex demodulation, beam forming and replica correlation) over 600 MOPS (million operations per second) sustained computing power could be shoehorned into a single 6U VME slot. The provision of two FPDP ports per DSP board, for separate input and output data paths, meant that an effective data throughput of 2.5 Gbits/s could be supported.

Figure 1 shows an active-passive hull sonar receive processing system developed using a set of COTS products based on these techniques. The system digitized 216 analog hydrophone inputs at 18 kHz sample rate by using seven 32-channel, 24-bit ADC boards. Beams could be formed using any 72 elements and three DSP cards could produce over 36 simultaneous beam outputs. Two further DSP cards provided low pass filtering of passive beams and demodulation of active beams. An optional single DAC card provided up to 32 analog beam outputs. Buffer cards were used to route beam data to the sonar post-processor either via VME64 or FPDP interface.

Impact of Technology Advances

The spectacular growth of the personal computer market over the last decade has had a profound influence on sensor processing system design since it has been a major driving force in semiconductor technology improvement. This has driven down component costs and also led to significant improvements in processor architecture and speed, signal interface data rates and data acquisition silicon performance.

Consumer interest in high-speed serial interfaces started with the introduction of FireWire and USB ports to provide a low-cost, high-speed and flexible way to attach computer peripherals. At around the same time, low voltage differential signaling (LVDS) technology was originally proposed as a “future-proof” means of providing inter-device communication because its small amplitude and low DC offset could cope with anticipated future reductions in CMOS supply rails.

After more than a decade of development, high-speed serial point-to-point interfaces based on LVDS techniques have finally emerged as a viable alternative to traditional parallel bus standards. High-speed serial standards such as PCI Express and Gigabit Ethernet have already been implemented in PC products thanks to highly integrated custom chips. However, the much lower volume military embedded market has only been able to exploit the benefits of high-speed point-to-point communication since serial fabric bridge silicon and sophisticated FPGA core and I/O functions have only quite recently become available.

Acoustic System Design

COTS-based sonar systems are normally operated in a benign environment and so the current generation designs adopted PC-based technology and a more distributed architecture in order to minimize cost while maintaining or improving performance.

Hydrophone data acquisition today uses a synchronized array of multi-channel ADC boards, controlled by a local CPU via a PCI-based backplane and housed in a rack-mounted 19” chassis. The digitized datastream is then transported via high-speed links to a separate data processing engine, typically a networked array of high-end PC servers.

Applying state-of-the-art technology to the multi-channel data acquisition function has led to the creation of a new concept: the acoustic acquisition server, a high-performance networked system component that radically reduces sonar system size and cost by packing up to 192 analog I/O channels into a single 19” rack-mounted, 1U enclosure. The server uses Gigabit Ethernet as an LVDS high-speed serial point-to-point interface to transfer two-way data and control information to or from a remote system controller, as illustrated in Figure 2.

In this example, the system controller, which incorporates the digital data processing engine, communicates with each acoustic server via Ethernet. Data flow uses UDP since it is a low-latency, reduced overhead transport method and can handle the data throughput of an acoustic server fitted with its maximum number of I/O channels in a low-frequency sonar application. The use of a managed Gigabit Ethernet switch offers greater flexibility in how UDP packets are routed. For example, during a beam forming operation, packets from one or more acoustic servers could be multicast to a subset of system controller processors. Remote configuration and status monitoring operations for each acoustic server are all performed using SNMP transactions.

Figure 3 shows a simplified view of the 1U acoustic server architecture. Internally, the design of the acoustic server has been optimized to provide high-performance, high-speed signal conversion capability for up to 192 channels of analog I/O or 240 channels of digital I/O using any combination of four I/O modules of three types. Each of the I/O modules slots is assigned a unique UDP port number, allowing for distributed processing such as forming partial beams using multiple distributed data processing engines.

Each I/O module communicates via two bidirectional high-speed serial links to the embedded controller motherboard. This provides sufficient bandwidth to operate an analog input module with 48 state-of-the-art performance, 24-bit ADC chips running at a sample rate of up to 2.5 MHz.

At the heart of the embedded controller is the FPGA-based data management and processing engine, which uses the Aurora protocol to manage I/O module data transfer, IP cores to implement the dual redundant Gigabit Ethernet interface, an embedded Linux-based software subsystem to control all functionality of the acoustic server and core logic to create a variety of hardware features used in normal operation and for test purposes. The 1U acoustic server development has been enabled by today’s technology. This becomes clear when you consider that a single high-speed serial link can handle the maximum throughput of the FPDP interface used in the first COTS sonar solutions.

Radio System Design

Military radio and radar systems require sampling and real-time digital processing of a small number of high-bandwidth analog channels and generally operate in a harsh environment. VME-based COTS components are widely used in rugged applications and now come equipped with high-speed serial links via the P0 connector. However, the bandwidth available for backplane communication is constrained by the limited availability of P0 signal pins. The beam forming application example in Figure 4 illustrates this problem.

In this architecture, a beam is formed from six channels of data, sampled at 200 MHz by three dual channel, 12-bit ADC mezzanine cards, each connected to a dual FPGA host processor card via an XMC connector. Each FPGA processor card is locally connected to two quad DSP processor cards via 2.5 Gbit/s StarFabric links and to other FPGA processor cards via 2.5 Gbit/s MGT links.

Although the RocketIO lanes of the XMC interface are capable of transporting raw ADC samples at 400 Mbytes/s per channel to each of the dual FPGA processors, the backplane serial fabric is not capable of supporting this data rate. One solution is to design the system architecture so that the data rate is progressively reduced to a level that is compatible with the backplane signaling rate. In this example, this approach was feasible by using the onboard FPGA resources of the ADC mezzanine card and the dual FPGA card to preprocess the data. However, this technique may not be viable in higher data rate applications.

Future Developments

The complexity inherent in processing sensor-acquired data has led to the increasing use of highly scalable, very high-performance multiprocessor systems. However, developing sophisticated applications for such environments can be enormously challenging, and this has resulted in advanced software tools coming to market that are designed to accelerate the development of complex signal processing applications, providing the ability to reconfigure or scale the system to meet future application demands and delivering seamless integration between the single board computer, signal processing and sensor I/O.

In hardware, it seems likely that the VITA 46/VPX standard will become widespread as the architecture of choice for high-performance back-end sensor processing because of the substantially superior throughput of which it is capable when compared with VMEbus-based systems. VPX provides backward compatibility with VME and PMC/XMC products and features a new, 7-row, high-speed connector with defined zones for VMEbus, serial fabric, XMC differential, PMC I/O and local I/O signals with the option of 3U and 6U form-factor boards. The 6U VPX connector provides for up to four ports of serial fabric per board, each port consisting of four 2.5 Gbit/s bidirectional links, and additional zones are reserved for up to two XMC cards to connect directly with the backplane. The VPX implementation of the beam forming application described previously would offer a 2.6x increase in serial fabric throughput that, coupled with the use of a mesh-connected topology between identical processor boards and the XMC mezzanine cards, would deliver a level of performance well beyond that of which early signal processing systems were capable.

Advances in technology and the demands of the consumer and military markets have brought about a revolution in system design methodology. The back-end management and processing of sensor-derived data has become steadily more sophisticated and more demanding with advances in hardware and software enabling the development of new applications—and new applications spurring the development of new generations of hardware, software and system design. It is a trend that looks very likely to continue.

GE Fanuc Embedded Systems
Towcester, UK.
+44 (0) 1327 359444.