RTC Magazine

Mezzanine cards have played an essential role in real-time embedded systems since the earliest days of SBCs and standard backplanes. They offer a wealth of specialized signal interfaces, data converters, connectors and transceivers along with dedicated engines for protocols, networks and signal processing. Standardization of the mechanical and electrical characteristics of these mezzanine cards enables system integrators to deliver specialized, high-performance embedded applications by judiciously combining open-architecture I/O products with processor boards.

Making its debut in 1994 as the IEEE P1386.1 standard, the PCI mezzanine card (PMC) was successfully adopted for both commercial and government electronic systems. Based on the mechanical specifications for the P1386 common mezzanine card (CMC), it included three 64-pin connectors to support a PCI bus interconnect to the carrier board, as well as a fourth 64-pin connector for user I/O.

During the next decade, important extensions to the PMC standard included conduction-cooled versions for severe environments, pin definitions for P4 I/O and the adoption of the processor PMC (PrPMC) specification.

When a proposal for standardizing gigabit serial switched fabrics shook the embedded computing community in 2002 as part of the VME renaissance, a natural extension of that technology to PMC modules was inevitable. Defined as the VITA 42 Switched Mezzanine Card (XMC), the XMC specification extends the PMC card by adding new connectors to support gigabit serial interfaces plus a growing list of alternative I/O standards.

VITA 42: A Mezzanine for All Seasons

The hallmark of any successful standard is that it continues to evolve with technology, and none offers a better example than XMC (Figure 1). The VITA 42.0 base specification includes general information, reference and inheritance documentation, dimensional specifications, connectors, pin numbering and primary allocation of pairing and grouping of pin functions. This document is still designated as a draft document, but it was released for trial use for an 18-month period that ends in March 2007. Recommendations gathered during the trial will be used to produce a final released specification.

XMCs can be single- or double-wide modules that use a pin-socket connector with 114 pins arranged in a 6 x 19 array. A single-width XMC can have one or two connectors with pin functions (Figure 2). A double-width XMC can have up to four connectors.

To support gigabit serial interfaces, both P15 and P16 connectors define 10 full-duplex differential pair lines. The VITA 42.0 base specification does not dictate signal types, data rates, protocols, voltage levels or grouping for these signals. Instead, it wisely leaves that up to the several sub-specifications that follow, allowing XMCs to evolve as new standards emerge.

In fact, contrary to the fundamental mission of supporting serial interfaces, the first sub-specification, VITA 42.1, defines these same pins for Parallel RapidIO. Although VITA 42.1 is approved and fielded, few vendors have embraced this standard and have instead opted for the more popular serial protocols.

VITA 42.2, 42.3 and 42.4 define true serial switched fabric protocols for Serial RapidIO, PCI Express and HyperTransport, respectively. The first two are already approved and beginning to appear as mainstream choices for a widening range of board and silicon vendors.

In fact, two major silicon vendors have announced new processors well suited for embedded computing applications that incorporate serial interfaces and protocol engines right on the chip. Texas Instruments offers the TMS320C6455 DSP processor with Serial RapidIO, while the Freescale MPC8641 includes both PCI Express and Serial RapidIO interfaces. These native interfaces simplify carrier board design and significantly boost peripheral I/O transfer rates by taking advantage of XMC modules.

VITA 42.5 defines the popular Xilinx Aurora protocol for use in XMC. This lightweight link-layer protocol is quite attractive for XMC modules because many XMCs only need to move data from a dedicated source, such as an A/D converter, to a dedicated destination, such as memory on a processor board. The extra protocol layers necessary to support a full switched network and routing can significantly reduce the payload data rate and add complexity and cost at both ends of the link. This standard is still in the definition phase.