High-Speed and Hybrid Backplanes
Trends in High-Speed Backplane Design
As backplane designers begin eyeing speeds of 25 Gbits/s and higher, new architectures, board materials and silicon may be required, as well as the evolution of interconnect techniques and attachment methods.
DAVID HELSTER, TYCO ELECTRONICS
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Backplane design is typically driven by performance, cost and functionality influences. Often, the resulting design calls for balancing one or more of these drivers to meet overall objectives, since one driver has some effect on the others. Soon after a specific approach to backplane design is selected, designers must specify the requirements for components and other items, such as high-speed backplane interconnect (Figure 1).
Connector manufacturers typically do not wait for the final interconnect requirements before determining how well a new connector will work with new backplane characteristics, such as speed, silicon and chassis. Instead, they collaborate with silicon developers and backplane designers and manufacturers, as well as electronic manufacturing service providers. This collaboration often runs in parallel to the development and selection of silicon, as well as other stages in the design process such as modeling.
Of course, when it comes to high-speed backplane design, some of the more noteworthy trends deal with speed. Backplane designers may consider changing the backplane’s architecture to obtain higher speeds. Other factors include materials and the future-proofing of backplane designs. Hybrid backplanes, regardless of their definition, are also subject to these trends to a certain degree and are likely to influence future generations of backplanes. Regardless of the particular backplane design, it usually has some type of influence on the interconnect design.
Getting More Speed from Board to Board
By definition, high-speed backplanes fill the need for high-speed applications and their designers are under continuous pressure to increase speed. Not long ago, the benchmark for high-speed backplanes was 3 Gbits/s. Now, designers are implementing 6 and 12 Gbits/s and even looking toward 25 Gbits/s. The real question, however, deals with how the high-speed design will be facilitated.
In connectors, it is difficult to identify one specific change that occurred to get backplanes up to 3 Gbits/s. At this speed, designers made changes on the backplane and used existing shielded connector technology. Many aspects of the backplane changed, but only in relatively small ways. The challenges in designing for high speed are how to effectively manage the combination of factors that make high speed work, as well as balancing all factors in the backplane design to get better performance while maintaining acceptable levels of cost and ease of manufacturing. Higher-density interconnect solutions, lower noise methodology and even smaller connector pinholes may all result in better performance. Additional considerations that figure into the speed and performance equation include silicon, signal distance, material types and board thickness.
As speed and performance requirements increase, more design techniques are required to accommodate them. Silicon developments that incorporate sophisticated equalization techniques can overcome some of the hurdles to making systems function at higher speeds. If the silicon is advanced enough, it may allow lesser performance in other areas of the backplane, such as the board, connectors and other components.
Using higher-performance silicon may not be the only action required. Designers may also need to consider counter-boring vias on the board, or sacrificing density to allow multiple channels in and out of the backplane. However, by investing in higher-performing silicon with sophisticated equalization, high-performance connectors or high-grade materials may not be needed on the PCB.
Speed and density are interdependent and continue to be driven by throughput. So the need to get, for example, 100 Gbits/s from one board to another can be accomplished by running 10 lanes of 10 Gbits/s, 20 lanes of 5 Gbits/s or 40 lanes of 2.5 Gbits/s. Clearly, density and speed work together and can drive connector design. If more throughput is required, and there is enough space in the backplane, the highest speed connector may not be needed.
In contrast, if space is limited more speed is required to get the same amount of data through less space, and a higher-performing connector is needed. This tendency influences backplane design lifecycles, because speed and density can only increase until no physical space remains to grow or expand the backplane. The development of modular connectors emerged as a secondary result of scaling density and speed on the backplane.
Jumping from 3 Gbits/s to 6 Gbits/s involved mainly tweaking the backplane in various areas. The effort was somewhat similar to the activity needed to achieve 3 Gbits/s, but a little more extensive. However, real challenges arise all around the backplane when moving to 12 Gbits/s. Backplanes that take speeds to 12 Gbits/s also raise connector performance requirement issues.
The main changes in connectors when moving from 3 Gbits/s to 6 Gbits/s required manipulating additional performance factors. These included less noise, better impedance control and better board attachment. But the shift to 12 Gbits/s requires designers to use additional techniques, such as changes in silicon, board materials, density and architecture. To get to 25 Gbits/s and higher, refinements to current methods may be required, or it could be that entirely different methods and technology will be needed. Some even speculate that a complete overhaul in backplanes as we know them could occur.
Although backplane designers have figured out 12 Gbits/s fairly well, requirements for 25 Gbits/s are purely hypothetical. First, new silicon is probably needed, since existing silicon is not expected to achieve this speed. This next-generation silicon could be developed so that it avoids the electrical issues encountered at 25 Gbits/s by building upon existing silicon’s sophisticated equalization techniques. Other questions, such as the near-term profitability potential of such products, cloud the issue a bit.
Speeds of 12 Gbits/s are probably fast enough to meet near-term market needs, but some in the industry see a need to develop faster backplanes with links of 25 Gbits/s up to 100 Gbits/s. While these links are largely I/O in nature and can be handled primarily by fiber, more throughput from the I/O will necessitate haste in developing backplanes of 25 Gbits/s and higher. The major question that remains for backplanes of the future is how designers will get from 12 Gbits/s to 25 Gbits/s and beyond that at the board-to-board backplane level. Designers will also be contemplating the move from 25 Gbits/s to 100 Gbits/s and its complexities.
Trends in High-Speed Backplane Architecture
Traditional high-speed backplane architectures work fairly well and allow acceptable performance at current speeds. But recent developments in how topologies are used and implemented are changing some conventional thought about connectivity.
An emerging, although not new, method is orthogonal architectures. These are a variant of traditional switch configurations in which each fabric card has a star topology. It is accepted that having two stars on a backplane is a complicated issue, and moving to three stars complicates things even further.
But with an orthogonal architecture, complex interconnectivity is simplified. Orthogonal applications twist backplanes, line cards and connectors, both literally and figuratively. An orthogonal, or cross-connect, architecture involves mating a front card vertically with a mid-plane interconnect that serves as a pass-through to another back card that is twisted 90° compared to traditional backplane/daughter card arrangements (Figure 2).
In addition to simplifying the interconnect, orthogonal architectures also improve electrical performance. Since they do not have mid-plane traces, the result is less electrical loss. However, orthogonal architectures are not suited to all applications. Since they use a mid-plane arrangement, line cards must be accessible from the front and rear of the chassis, which is not possible in all cases. Where they can be used, orthogonal architectures offer reduced board thicknesses and layer counts. To accommodate them, connectors have changed to facilitate the 90° orientation on the mid-plane and line card. This is most notable on the mid-plane, since conventional backplanes do not have 90° connections.
It should be pointed out that the thermal profile of an orthogonal mid-plane poses different challenges from that of a traditional backplane, since line cards are arranged horizontally and do not have the natural venting possessed by vertical line cards.
The PCBs used in backplanes are evaluated regularly, particularly for cost and performance. The pursuit of higher speed and performance on the board revealed the advantages of counter-bored vias, which have influenced connectors as this method of improving board performance gained acceptance. Designers have previously manipulated board materials to help optimize speed and performance, but board material selection is becoming a primary concern.
Increasingly, high-speed backplane designers want to future-proof their systems so that more and more backplane designs can accommodate the higher speeds expected later in their design lives. To facilitate this, designers may use some components, such as connectors, capable of operating at higher speeds than those at which they are currently used. Designers should balance the need for future-proofing with the backplane’s expected lifespan. This is usually accomplished by using a connector with the highest speed capability on the backplane, then letting the mating line card interconnect evolve to the expected higher speeds. In this scenario, the backplane’s lifecycle is assumed to be longer than that of less costly, easier-to-replace line cards.
Other trends in backplane design have a lesser or indirect impact on interconnects, such as quad routing. Here, the columns of signals are spaced far enough apart so that two differential signal pairs can pass between them. For applications that can sacrifice density, this increases the amount of signal placed on a single layer, resulting in thinner boards, fewer layers and, consequently, lower cost.
Alternatively, some designers may invest in better board materials in addition to quad routing, providing an even higher-performing line card or backplane. Additionally, with potentially thinner boards, shorter via stubs result and counter-boring may not be necessary. With shorter via stubs, signal performance is better, and if counter-boring is not required, manufacturing costs are reduced. In the end, higher-performing connectors are probably better suited for quad-routed applications and enhance overall backplane performance.
Connector Board Attachment Methods
Another key issue is connector board attachment methods. Press-fit is the known, reliable method for attaching a connector to the backplane, and has allowed acceptable performance to date (Figure 3). Alternatives include surface-mount (SMT). Currently, the use of SMT connectors in backplanes is limited because of considerable manufacturing concerns, including co-planarity, inspection and repairability. However, some speculate that SMT connectors may offer a better board attachment method for backplanes because of possible improvements in electrical performance, such as reducing the size of, or altogether eliminating, board vias to the layers in some applications.
The main part of the discussion regarding attachment methods involves the performance improvements that SMT might provide and whether a transition to SMT would allow enough improvements to counterbalance cost, manufacturing process changes and industry acceptance issues. Others caution that improvements will be marginal and further development is required, but with many seeking a way to get to 25 Gbits/s, SMT is not off the table.
The gradual movement toward higher-speed backplanes results from many influences. While improvements in speed and performance are top priorities, some questions remain about how to get there. Certainly, connectors will play a role in many of the future needs of high-speed backplanes. A gradual evolution in connector performance and design is expected. The development of new silicon to power backplanes will undoubtedly drive much subsequent design activity. Further, with the new silicon, additional, more functional topologies may emerge that will help improve performance. Materials and other components will likely follow with innovations to accommodate the new performance requirements. After the first successful attempts to get to 25 or 100 Gbits/s, all participants will begin developing new tools to tweak and optimize each respective part of the backplane, and the cycle will continue.