RTC Magazine

Since its adoption in the early 1980s, the VME architecture has evolved continuously, and remarkably successfully, to keep pace with the improvements in microprocessor and communications technology. In the early 1980s the world was learning about PCs that used 5 MHz CPUs, 640 Kbyte RAM and the ISA bus. Now we are growing used to dual core 2 GHz CPUs with 4 Gbyte RAM and PCI Express. As the CPU capabilities have grown, so must the communications between them, particularly in backplane systems utilizing several intelligent boards. Parallel bus technologies have been stretched so far, but now the future is plain—serial interconnects with ever-increasing bandwidth are the choice for the future. VME has willingly embraced this change with the introduction of three major standards: VITA 31, VITA 41 and now VITA 46.

VME has moved from the 20 Mbytes/s backplane speed where it began, through 40 and 80 to 320 Mbytes/s offered by 2eSST technology. Each step has pushed the limits a little more, and stretched the backplane signal timings so that skew or signal quality effects are increasingly causing concern for further enhancements. Serial interconnects reduce the scale of these problems significantly, and allow not just improved speeds now (in excess of 1 Gbyte/s), but the promise of significant increases to come. This is countered to some extent by increased latencies and overheads associated with the serial protocols (see sidebar “The Good and Bad Sides of Serial Interconnects,” p.36).

The boards in VME systems, as in other types of systems, have become more and more intelligent over time, and with this intelligence the level of inter-board communications has changed. As an example, consider an advanced radar system using several VME CPU boards to collect and process imaging satellite data via multiple DSP-based acquisition boards. Figure 1 shows the way these boards used to be connected for this real-world application. The DSP boards acquire data from the satellite receivers, then process the data to filter noise and to create digitized information that is passed via VME bus to one or more CPUs, normally located in the same VME chassis. The user interface is provided by an external PC connected via a LAN. In this situation, the VME bus provides both the control and data planes for the acquisition boards. As a result, in higher-end applications, the number of VME slots used by the DSP boards, together with the total VME bus bandwidth requirements, limits the total processing capacity of the system.

Now consider Figure 2, where the DSP boards have been replaced by FPGA PMC boards on VITA 41 baseboards, and the main CPU board has been replaced by a much more powerful unit using a very fast dual-core processor. The data processed by the FPGA boards is now passed via backplane Gigabit Ethernet connections to a CPU board in the same chassis. The VME bus remains in use as the control plane while the VITA 41 serial interconnect is used as the data plane. The system connects via the chassis switch boards to the LAN, which hosts the PCs providing the user interface. In this system, flexibility is greatly improved by utilizing the in-system LAN to provide both the internal and external connectivity, allowing CPUs or additional FPGA engines to be added either inside the chassis or even in an entirely separate chassis. Splitting the control and data planes for the FPGA boards also improves responsiveness to control functions by minimizing interference from data transfers.

In adopting a serial interconnect, the traditional backplane “bus” is no longer present. Several interconnection topologies are possible, but the most common are the star and dual star configurations shown in Figure 3. The obvious complication with these topologies is the need to include one or two additional switch boards, which adds to the costs and of course lowers the system MTBF. However, a dual star configuration also provides multiple interconnection paths between boards, potentially improving overall system reliability. An alternative topology, also shown in Figure 3, is the mesh, which allows boards to directly connect to each other without using switch boards. This improves the cost but makes the implementation of multiple interconnection paths much more complex.