RTC Magazine

Real-time data recording and playback is an important capability in many high-performance processing applications, such as military sensor processing. To enable this capability, it is highly desirable to leverage the rapid technological and economic advances that have been made in mass-market IT applications. The demands of these applications have led to a proliferation of cost-effective, high-performance, high-capacity data storage devices, with well-defined interfaces based on open standards protocols such as SCSI, Fibre Channel and Serial ATA.

However, typical high-performance processing applications offer some specific challenges that make it more difficult to extract the required performance and functionality from standard storage interface implementations. There are two challenges frequently encountered in the high-performance sensor processing application space.

First, sensors such as radar front ends or camera systems may generate very high bandwidths of digital data, and typically the storage system must offer real-time recording and playback capabilities. Data rates in excess of 3 Gbytes/s from a single sensor channel are not uncommon. The second challenge is the fact that embedded applications, especially those in rugged operating environments, may be constrained in terms of size, weight and volume, as well as by the need to operate reliably over extended periods of time.

Mass-market storage interface implementations typically utilize dedicated chipsets and standard storage interface circuit boards designed to operate within server or desktop computer environments. Deploying such devices within embedded systems will not necessarily address these systems’ bandwidth efficiency and size constraints.

Using FPGAs to Implement Storage Interfaces

Rather than using standard chips and interface cards to implement storage interface solutions, it is possible to deploy state-of-the-art FPGAs to realize the storage interface as part of a complete system-on-chip (SoC) solution.

FPGAs are increasingly employed in high-performance processing systems to provide both a flexible interface component and a high-speed data processing resource. These devices now also include a rich set of on-chip hardware resources that can be used to build storage interfaces such as Fibre Channel, Serial ATA and InfiniBand.

For example, some devices in the Xilinx Virtex 2 Pro, Virtex 4 and Virtex 5 FPGA families contain multi-gigabit transceiver (MGT) resources. These resources can be employed to implement the physical layer of storage area interfaces such as Fibre Channel. Larger FPGA chips contain up to 20 such MGT resources, allowing the implementation of multiple storage interfaces on a single device.

Devices in these FPGA families also contain embedded PowerPC processing cores that can be employed to implement the more intricate parts of the storage interface protocol layers using software.

By coupling these types of hardware resources with the very large configurable logic arrays found on FPGAs, it is possible to design storage interface implementations optimized to exactly meet the needs of the target application. This is done via custom hardware and software implemented in the FPGA.

Furthermore, due to the degree of flexibility and reuse offered by implementing the storage interface entirely within the FPGA, it is relatively easy to create optimized solutions for a wide range of different real-time applications. For example, a Fibre Channel storage interface core can be deployed in one application where input data is being received from an A/D converter device. The same core could be easily retargeted for an application that receives input data from some form of high-speed digital interface.

All of this can be achieved within the confines of a single physical chip, alongside other system functionality such as digital signal processing if required. Consequently, the FPGA approach to implementing the storage interface is also attractive in terms of its size and system reliability improvements.

Two different types of systems may be examined to show how storage interfaces on an FPGA can be used to realize data storage functionality for high-performance, real-time embedded applications with a range of constraints and requirements.

FPGAs in a Serial FPDP Compact Digital Data Recorder

Serial FPDP (SFPDP) is a popular interface standard widely used in high-performance systems. The protocol has been kept very simple in order to support high-bandwidth, low-latency transfer of data streams between remote nodes in a system. A data stream is serialized onto a fiber optic link that also enables transfer of data over long distances. A typical application of serial FPDP would be to interface a front-end sensor, such as a radar antenna located on the outside of an aircraft, to a remotely located processing or display system inside the aircraft’s cockpit.

An FPGA can be used to implement a complete system-on-chip solution that converts an SFPDP data stream to a Fibre Channel storage interface to a Fibre Channel disk or RAID system (Figure 1).

In this case, the complete system is implemented using a single FPGA device, a Xilinx Virtex II Pro P50, equipped with four fiber optic transceivers for converting the high-speed serial signals from the MGTs in the FPGA to fiber.

Firmware in the FPGA is used to provide more than one type of functionality. It can, for example, implement the SFPDP protocol. Two sets of firmware can be instantiated, using two of the available MGTs, to achieve up to double the bandwidth available from a single SFPDP link. Firmware can also be used to provide optional, high-speed processing of the data received or transmitted via the SFPDP interface.

A third type of functionality is the implementation of a Fibre Channel storage interface. Two MGTs are employed to provide two high-bandwidth Fibre Channel links to two hard disk systems, doubling the I/O bandwidth available for real-time recording and playback.

The Fibre Channel storage interface is a well-defined subsystem inside the FPGA. It is cleanly decoupled from the rest of the system by using a FIFO buffer arrangement. The FIFO serves the dual purpose of managing the ebb and flow of data to and from the storage interface while providing a simple, easy-to-use, high-bandwidth interface to which the SFPDP application can connect its data.

The Fibre Channel storage interface function utilizes the embedded PowerPC cores in the FPGA to execute the control and management logic required for the Fibre Channel protocol and the disk filing system. These functions are well suited to software, rather than hardware, implementation due to their complexity. In addition, the processor provides sufficient performance to execute them at the rate required for the Fibre Channel protocol.

At the same time, the FPGA also provides dedicated, customized hardware data paths to allow the real-time data to be streamed directly to and from the disk systems. This optimal combination of resources in the FPGA yields a system that is extremely compact, yet sufficiently powerful to support real-time data transfer for many applications.

FPGAs in a Scalable Storage Interface System for Very High-Bandwidth Analog Signals

There are many examples of embedded processing cards that combine very high-speed A/D and D/A converters with FPGAs to provide real-time DSP platforms for high-bandwidth signals. Real-time data recording and playback is a common requirement in such systems. However, some currently available commercial A/D cards operate at sample rates in excess of 2 GHz, which means that a real-time data storage system may have to cope with data bandwidths in excess of 3 Gbytes/s for a single channel.

Employing multiple disk arrays in parallel is an obvious way to add more recording and playback bandwidth to the system. An FPGA implementation of the storage interface offers the possibility of multiple instantiations of the storage interface in a single chip. This delivers a compact means of providing storage interfaces to multiple disk arrays. This is enabled primarily by the availability of multiple MGT resources on a single FPGA chip, each of which can be populated with multiple instantiations of the firmware to drive it as a Fibre Channel, or other, storage interface. Further scalability via multiple FPGA devices can improve available storage bandwidth even more.

An FPGA-based implementation of the storage interface can been used to scale the recording bandwidth sufficiently to support recording and playback of data from a 2 gigasample/s A/D and D/A card (Figure 2). In this example, two commercially available cards are connected together via a high-speed interconnect such as a VXS backplane. One card hosts the A/D and D/A converters. The second card provides multiple FPGAs, each with a number of fiber optic ports connected to its MGTs, which are used to implement the storage interface functionality.

The Fibre Channel storage interface firmware is instantiated multiple times in each FPGA, to support four Fibre Channel connections to RAID disk arrays for each FPGA. The parallel RAID array arrangement provides sufficient bandwidth to support real-time recording or real-time playback of wideband signals at 20 Gbits/s from the A/D and D/A card.

By employing the FPGA firmware implementation of the storage interface on commercially available FPGA hardware platforms, it is possible to achieve the storage bandwidth required for a very challenging real-time application.

System-on-Chip Approach Is Scalable, Boosts Reliability

Efficient implementation of storage interfaces is a challenge for real-time embedded processing systems that require real-time data recording and playback capabilities. Data bandwidths are high, and in many embedded applications, size and reliability constraints can be difficult to achieve with conventional interface cards.

A novel approach can be employed that uses FPGAs for implementing storage interfaces, such as Fibre Channel, as part of a complete system-on-chip solution. This approach has a number of advantages.

Hardware and software can both be tailored via programming to suit specific requirements, enabling high performance with low development effort. Storage interfaces become part of a single-chip solution for a complete processing system, saving space and improving reliability. Finally, FPGAs enable multiple storage interfaces to be supported with a single chip, allowing systems to be highly scaled to meet increased bandwidth requirements.

TEK Microsystems’ JazzStore SoC technology offers an FPGA implementation of a Fibre Channel-based data recording system (Figure 3). This SoC complements the Tekmicro Jazz and Quixilica FPGA-based hardware product ranges, allowing the provision of real-time data recording/playback functionality in a wide range of demanding real-time applications.

TEK Microsystems
Chelmsford, MA.
(978) 244-9200.
[www.tekmicro.com].