High-Speed and Hybrid Backplanes

VXS Processor Mesh Architecture: Powerful, Flexible, Compatible

Although the VXS Processor Mesh architecture does not define any new backplane pin assignments beyond those already defined within the VITA 41.0 base specification, bandwidth capabilities exceed 112.5 Gbits/s of aggregate throughput within the processing mesh in a single chassis.


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VMEbus has morphed once again. One of the most promising developments is VME Switched Serial (VXS), also known as VITA 41. Like many of today s specifications, there are a host of subsidiary documents to support the platform, which is VITA 41.0. Other specifications define various signaling protocols ”such as InfiniBand, RapidIO, Ethernet and PCI Express ”all of which can utilize a single backplane physical architecture that is defined by the base document.

The latest VXS innovation is the VXS Processor Mesh specification, VITA 41.7, developed by Elma Bustronic. This new backplane architecture, first demonstrated at BusBoard 2006 in Long Beach, will provide a higher level of connectivity for VXS than has ever been previously considered. Perhaps its major significance is the fact that it does not define any new slot mechanics, connectors or channel definition.

VXS defines within VITA 41.0 two new classes of cards: payload cards and switch cards. The payload card implements a single new differential connector in the P0/J0 position that exists on conventional VME64x cards today. The switch card defines a slot that is filled top to bottom with the new high-speed, differential MultiGig connectors.

Standard Slots, Flexible Configurations

Processor Mesh defines a set of five fully meshed switch card slots, with four bi-directional channels ”a total of 32 differential pairs ”between each slot and every other slot. This configuration became a reality when a VXS switch card vendor began discussing its application with Elma Bustronic. The two switch slots on a conventional VXS dual-star backplane are enough for most applications. However, in an especially challenging requirement, as many as five of these processor boards would probably be needed. In addition, a greater level of connectivity between each of these powerful cards was desirable.

The challenge was how to integrate five switch cards into a larger VXS system in a useful way that would be flexible enough to support the widest range of other, similar applications. At the same time, the processing resources on those cards had to function at their highest capability. The result became VXS Processor Mesh. The new backplane topology integrates conventional VXS switch cards in a mesh configuration. Therefore, the switch cards are no longer connected directly to any payload cards, but only to other switch cards. The connection paths between each and every one of the four mesh slots consist of four direct, unswitched channels, which together offer a bi-directional 40 Gbit/s path. They could also be used as 32 differential pairs in a single 80 Gbit/s unidirectional pipe.

This meshed section is for special processes and is in addition to the two conventional dual-star fabric slots that are still required to support the A ? and B ? fabric connections to the payload slot in a system (Figure 1).

With this new architecture, VXS backplanes are no longer limited to a single pair of fabric switches. Most importantly, the payload cards and switch cards in VXS Processor Mesh can be the exact same cards that are used in the classic dual-star VXS systems.

VXS supports the continued use of existing VME64x cards. This is particularly important when special cards have been developed by end customers to serve as a custom interface to a special type of sensor or output device.

For example, if those cards used a 2 mm HM connector in the P0 position, it can now be replaced with a single differential MultiGig P0 connector that supports 20 times the bandwidth of the existing 2 mm HM center connector. Both Processor Mesh and Payload Mesh VXS backplanes have been produced with one or more slots equipped with the legacy 2 mm HM center connector, in order to accommodate existing VME64x cards that do not currently justify being redesigned (Figure 2).

FPGAs Prefer Direct Connections

Another consideration is the fact that many high-performance VXS cards are FPGA-based. FPGAs from Xilinx, Altera and others are most effective when used in point-to-point topologies. FPGA-based designs require less code and deliver more performance when used with direct, streaming serial protocols such as Aurora and SerialLite. Although the VXS standard was designed to support a switched fabric topology, VXS backplanes will not always be used for this purpose.

The core VXS document, VITA 41.0, is written to support a switched topology that might comprise 18 payload cards and two fabric switches. Typically, a dual-star backplane links any two payload cards through one of the two fabric switches. A single-star architecture, or the same dual-star architecture, supports point-to-point applications perfectly when the processors are located on cards in the switch slots. When each payload is designed to communicate only with the processing card, there is no need for a conventional fabric switch.

But what if an application will require more processing cards, for instance, three, four or even five? This is where VITA 41.7 comes in. It enhances the VXS platform by supporting an array of up to five processing cards in an arrangement that is ideal for high-bandwidth, point-to-point signaling. Additional features of the topology allow this specialized processing bus segment to be integrated with the rest of the backplane in a very flexible and scalable manner.

The MultiGig connector is used in positions J1 through J5 in a Processor Mesh backplane. Connectors J2, J3, J4 and J5 provide enough channels to allow four channels of connectivity between each and every card in the mesh. Of the remaining channels in those four connectors, two channels are allocated to the center fabric channels and two channels are reserved for future I/O uses. The J1 backplane connector in the conventional switched slots, as well as in the Processor Mesh switched slots, provides all of the system signals for management and other functions. J1 also provides undefined pins.

Each 16-row MultiGig differential backplane connector in VXS switch slots supports six full channels. That means that the four fabric connectors ”J2, J3, J4 and J5 ”can support a total of 24 channels of point-to-point connectivity. In addition, there is a J1 connector that supports a wide array of slower system signals. The power connector is separate and provides 30 amps of +5 VDC for a total of 150W. At present, there appears to be no architecture that has more data transport connectivity than that provided by VITA 41.7. VITA 46, not yet released, does not provide for more channels, nor does it define a standard mesh implementation. Both PCI Express and CompactPCI Express can support a maximum of 16x bi-directional links.

AdvancedTCA, for example, does define a 16-slot mesh backplane with a single 10 Gbit/s channel between each of the 16 cards. However, the smallest redundant meshed application that is defined is a five-slot mesh, which can also offer four channels of connectivity between each of those meshed slots. This is exactly what VITA 41.7 now provides.

A Defined Platform Ensures Multi-Vendor Interoperability

The fact that the fabric slot has a fixed channel definition across all VXS subsidiary specifications ”including the new VXS Processor Mesh architecture ”is important to the development of VXS infrastructure. The efforts at maintaining compatibility in the VME standard ensured that a steady stream of new products would continue to be produced by a diverse community of card vendors. In the same way, the fixed slot definitions in VXS mean that vendors can be sure that the cards they produce for one application can be used in any other VXS backplane being developed.

In a typical VXS Processor Mesh backplane, the center fabric channels that are part of the basic dual-star architecture are carried forward onto fixed locations on each of the five processor mesh slots. This is to ensure application scalability.

VXS Processor Mesh is Scalable

One architecture that might be implemented within the meshed processor slots is a pipeline. In a pipeline topology, data is delivered to the first card in a series for computation. The results of that operation are then passed on to another card where a different processing algorithm is applied. This may be continued until the data has passed through each of the five cards. The final results can then be exported by means of the central fabric channels.

If the system vendor develops a new card that is more highly integrated, this card can replace two of the cards that were previously part of the pipeline. In some other architectures it might not be possible to have an unpopulated backplane slot, because there might be no alternate channel where data could be exported out of the pipeline. This would be the case if the designers did not provide identical support to each slot.

In another hypothetical situation, a system might be developed with the same set of five cards. In this scenario, the algorithm implemented on one of the cards might not be useful for a new type of data being processed.

Because VXS Processor Mesh provides the two fabric channels that connect each of the five meshed slots to the rest of the system, and because there are additional RFU pins that could be also used for I/O, the meshed switch slots are very flexible. Any card configuration would be supported whether it required only a single slot or the entire five slots.

This emphasis on standard slot pinouts for all switch card slots makes it possible for system integrators and backplane vendors to stock only a relatively small selection of all the different possible VXS backplane designs. Even if only a large backplane with a high number of slots is available off the shelf, such a backplane can be used if there is physical space to accommodate the unneeded slots.

VXS is Future Proof

Not every application will need all of the connectivity that the Processor Mesh architecture can provide. After all, most typical VXS applications do not require more processing than can be squeezed onto the two conventional VXS fabric slots.

However, the development of VXS Processor Mesh is a significant boost for VXS. With four 16x redundant mesh channels between each slot, no other architectures on the horizon have more connectivity. Providing both backward compatibility and a forward performance path, VXS Processor Mesh offers a great deal of flexibility.

Since VXS Processor Mesh defines a standard slot and at least three different backplane architectures, there will most likely be a large number of interoperable products available during the next year. For these reasons, VXS Processor Mesh has brought a higher level of performance to VXS, effectively future-proofing the entire VXS product line.

What Comes Next

With the addition of the Switchless Payload architecture, and now the Processor Mesh architecture, VXS implementers can expect to see a number of additional backplane designs. For instance, it has been clearly demonstrated that the three-slot switchless payload card mesh is not limited to a single set of three cards. Instead, it is quite possible to array as many as seven sets of these three slot meshes along a single VME backplane.

The same is true for VXS Processor Mesh. Although it is difficult to imagine an application today that would need such processing power, two or even three 5-slot mesh segments could be laid out on a single VXS backplane. In this case, I/O would probably have to come in via the front panel or be concentrated at the six remaining payload cards.

Elma Bustronic

Fremont, CA. (510) 490-7388. [].