Kontron
InterphaseINDUSTRY INSIGHT
CompactPCI and Switched Fabrics
Advanced Switching on CompactPCI Express
Advanced Switching can be used within CompactPCIe to allow multiple CPU boards and dynamically mapped I/O in high- performance, network topologies.
STEVE COOPER, ONE STOP SYSTEMS
Advanced Switching Interface (ASI) is an extension to PCIe that allows CPU-to-CPU communication and dynamic I/O mapping to work on top of the basic PCIe functionality. For multi-CPU systems, this provides a unification of the CPU-to-CPU communications bus and the I/O bus structure. This unification provides dramatic improvements in performance, system cost and fault tolerance. With CompactPCIe, ASI bridge and switch components becoming available in 2006, new systems that incorporate ASI within CompactPCIe are suddenly within reach.
CompactPCI was developed in 1996 as a standard bus structure that combined the cost-effective PC bus architecture (PCI) with the popular Eurocard industrial board form-factor. This combination quickly became the world s most popular bus structure for industrial, communications, military and test systems where PCI is used in a rugged form-factor. In 2005, the PICMG standards body defined a new CompactPCI specification that incorporates the new PCI Express (PCIe) bus in place of the original PCI bus.
The CompactPCIe specification replaced the P1 and P2 connectors with four connectors that provide the new PCIe bus as well as enhanced power capabilities to each board (Figure 1). The bottom connector provides high current connections for incoming power; the second and third connectors provide the PCIe differential pairs for multiple PCIe buses to be routed from each board to the backplane. The top connector provides specialized I/O signals for user I/O or for PXI extensions for instrumentation.
Since PCIe provides point-to-point connections, a switch is needed to connect the CPU to multiple I/O slots. Within the basic PCIe architecture a single CPU board is connected through a switch to multiple I/O boards (Figure 2a).
ASI within CompactPCIe
Advanced Switching Interface is a protocol that resides on top of the basic PCIe packets and adds additional routing information to each packet. This extra protocol allows the PCIe topology to be extended to support full network topologies that include multiple CPUs and dynamically mapable I/O, as shown in Figure 2b.
PCIe I/O boards can continue to be used unchanged. This is accomplished by mapping each I/O function to an individual CPU board. I/O board mapping is dynamic, initially being set during system initialization, but later being changed due to hot-swap events or CPU board failures that require re-mapping.
CPU boards need to have their PCIe bus signals converted to ASI-compliant signals before they can communicate within the network topology. This is accomplished by sending each PCIe bus from the CPU through a PCIe-to-ASI bridge component. The specifications allow this component to be placed on the CPU board or on the switch board. If the bridge component is placed on the switch board, then off-the-shelf CPU boards can be used unchanged within a tree or a network topology. In this case, the only element that changes between the tree and network topology is the switch board.
CompactPCI has built in flexibility in that its P3, P4 and P5 connectors are available for user defined rear I/O or secondary buses or interconnects. Several uses for these connectors have themselves become standardized. One of the most popular of these is PICMG 2.16, which defines how 1 Gbit Ethernet can be routed through the P3 connectors to a special 2.16 switch slot. This mechanism allows multiple CPU boards to intercommunicate via the Ethernet in a network topology. Split backplane solutions have extended this concept to allow multiple CPU domains (isolated CPU and I/O slots) to be integrated within a single system, with the CPU boards connected by Ethernet routed via 2.16.
ASI as an Upgrade Path for 2.16 Systems
ASI within CompactPCIe provides a particularly attractive upgrade path to 2.16-based systems. The advantages of ASI include 10x higher performance, lower costs and dynamic I/O mapping. A basic comparison between ASI and 2.16 solutions is shown in Table 1.
ASI performance depends on the lane width of the underlying PCIe buses. Typical systems will include two independent x4 PCIe bus interfaces from each CPU board. Each of these interfaces operates at 10 Gbits/s. Higher performance is achievable by boards that utilize x8 or x16 interfaces, or from the move to Gen 2 timing, which is expected to become available in late 2007.
Lower costs result from the combination of two buses (PCI and Ethernet in 2.16) into one PCIe bus that performs both functions. CPU boards don t need to drive the extra Ethernet ports into the backplane, and an expensive 2.16 switch board is eliminated. The CompactPCIe with ASI solution does require its own switch board, but this function provides both the I/O board fan-out and multiprocessor switching functions.
