RTC Magazine

RapidIO technology is a fast growing interconnect and fabric standard for embedded systems, providing increased performance, improved efficiency and lower cost. RapidIO technology is supported by a broad ecosystem of leading vendors with multiple vendors shipping production switches, endpoints, FPGAs, boards, software and systems. Serial RapidIO technology offers a high-speed physical layer that can be configured to match bandwidth requirements with different speed variants and numbers of lanes.

Serial RapidIO builds on the communication industry’s common roadmap at the serial physical layer, using a variant of IEEE 802.3 Xilinx 10 Gigabit Attachment Unit Interface (XAUI) today for 3.215 Gbits/s. For future 5 and 6 Gbit/s versions, it is using a variant of the work done on the Optical Internetworking Forum’s (OIF) Common Electrical Interface (CEI).

RapidIO architecture has no inherent limitations preventing it from scaling indefinitely into the future, following or anticipating industry requirements. RapidIO technology has evolved over the past five years to a full system dataplane fabric, with extensions completed and in progress for:

• RapidIO Flow Control Logical Layer Extensions Specification

• RapidIO Data Streaming Logical Layer Extension Specifications

• Phase I: Encapsulation and Traffic Management Framework

• Phase II: Advanced Traffic

Management

• RapidIO Multicast Extensions Specifications

• RapidIO Next Generation Physical Layer Specifications

A comparison of the data rates between the different modes of Parallel and Serial RapidIO is given in Table 1.

Flexible Physical Interface

The RapidIO logical packet description is defined to be physical-layer-independent. This means that the RapidIO protocol could be transmitted over anything from serial to parallel interfaces, from copper to fiber media. The first physical interface considered and defined is known as the 8- or 16-bit link protocol end point specification (8/16 LP-LVDS). This specification is defined as having 8 or 16 data bits in each direction along with clock and frame signals in each direction.

The 8/16 LP-LVDS interface is a source-synchronous interface. This means that a clock is transmitted along with the associated data. Source synchronous clocking allows longer transmission distances at higher frequencies. Two clock pairs are provided for the 16-bit interface to help control skew. The receiving logic is able to use the receive clock for re-synchronization of the data into its local clock domain.

Since the Serial RapidIO specification is only defined in the physical layer (RapidIO technology defines the physical layer as the electrical interface and device-to-device link protocol), most of the controller remains the same. As a result, much of the design knowledge and verification infrastructure are preserved (Figure 1). This eases system-level switching between parallel and serial links. During the initial development stages of the Serial RapidIO specifications the designers decided to preserve as many of the concepts found in the RapidIO parallel specification as feasible. The parallel specification includes the concept of packets and in-band control symbols.

These were delineated and differentiated by both a separate frame signal and an “S” bit in the header. In the serial link specification this delineation is accomplished using spare characters (“K-codes”) found in the 8B/10B encoding technique. In this way, the sending device indicates to the receiving link partner the start of a packet, end of packet or embedded control symbol using these codes.

Comprehensive Link Protocol

A unique feature of RapidIO technology is that packet transmission is managed on a link-by-link basis. In the past, with synchronous buses, a mastering device had to exchange handshake signals with the target device. These signals indicated whether a transaction was acknowledged and accepted by the target device. With an interface such as the RapidIO specification defines, it is not practical to rely on a synchronous handshake since the receive port of a link is decoupled from the sending port. Therefore, many interconnects have ignored this issue and rely on an end-to-end handshake to guarantee delivery. However, this has the disadvantage of preventing precise detection and recovery of errors and forces far longer feedback loops for flow control.