RTC Magazine

Advanced Switching is something of an extrapolation of PCI Express, borrowing its lower two architectural layers from the PCI Express specification, but diverging at the transaction layer and in the marketplaces it intends to serve. Whereas PCI Express has already begun to reshape a new generation of PCs and traditional servers, Advanced Switching is intended to proliferate in multiprocessor, peer-to-peer systems in the communications, storage, networking, servers and embedded platform environments (Figure 1).

The need for Advanced Switching (AS) essentially comes about as computing and communication platforms begin to converge by exhibiting increasing overlap in terms of the functions they serve. While PCI Express is clearly the interconnect of choice for the computing industry, a common interconnect with the communications industry seems logical and necessary, in order to keep development costs down, performance up and reduce time-to-market. By sharing the same physical and data link layers as PCI Express, AS leverages an in-place infrastructure and provides built-in cost savings by expanding a common ecosystem of IP, tools, services and foundries.

Starting with PCI Express

PCI Express is a layered, multi-lane, serialized evolution from the monolithic, parallel PCI/PCI-X system architectures. These layers include the physical layer, data link layer and transaction layer (Figure 2).

At the physical layer, an initial 2.5 Gbit/s dual simplex, point-to-point topology is specified, with future provisions to scale much faster. The PCI Express base specification calls for up to 32 lanes, although in current practice, developers are tending to build at no wider than 16 lanes, with most non-graphics development being designed at x1, x4 and x8 (pronounced “by one,” “by four,” etc.). Implementations at x2 and x12 are also specified.

All information moving across the link is in 10-bit byte format and most of this information is scrambled. Data scrambling is a process that encodes these bytes such that repetitive patterns are eliminated from the bit stream. Repetitive patterns can concentrate energy at specific frequencies, which generates EMI. Scrambling spreads energy over a wider frequency range, eliminating any nasty spikes.

Coming down through the stack, 8-bit data is scrambled first and then encoded to the 10-bit format before being serialized and sent out on the wire in LVDS form. On the other side of the link, the data stream is de-serialized, followed by a 10b/8b decoding and descrambling.

This 8b/10b scheme does result in an inherent 25% overhead, but considering the brute speed at which PCI Express operates, it’s essentially inconsequential. For example, at a x1 link width, aggregate PCI Express bandwidth is 500 Mbytes/s. At x16, bandwidth scales to a blistering 8 Gbytes/s. By comparison, legacy PCI running at 66 MHz and 64-bits wide, provides 533 Mbytes/s of raw bandwidth (Figure 3).

Beyond the obvious bandwidth advantages, it is important to note that PCI Express can move much more information around a system using much less real estate. A x8 PCI Express link provides 100 Mbyte/s performance, on a per pin basis. This provides advantages in power requirements, size and ultimately, cost. At the data link layer, mechanisms are in place to ensure data integrity by way of CRC checks, transaction sequencing functions and ACK/NAK protocols.

The PCI Express transaction layer will look familiar to those who have worked with PCI or PCI-X architectures, with some obvious additions. The familiar configuration, memory and I/O transactions are still there, with a new message transaction type being defined. Message transactions transport interrupts, power management information, vendor messages and error reporting mechanisms.

Address space will again appear familiar, although configuration space is extended from the 256 bytes used by legacy PCI to 4 Kbytes, and message space is added. New software must take advantage of this extended configuration space, but legacy PCI software, including OS, drivers and applications, will operate just fine in a PCI Express environment.

A Typical PCI Express Transaction

Moving a transaction, such as a memory read, from one PCI Express device to another involves all three layers on both devices. As the application initiates a transaction in one device, it is passed down from the transaction layer, through the data link and physical layers, and across the link to the receiving device. At the transmitting device, the data link and physical layers append various fields to the transaction, such as framing characters, CRC values and sequence information. On the receiving device, these physical and data link appendages are monitored for various purposes and are stripped away as the transaction moves up the stack, leaving purely transactional information to be consumed at the highest layer.