RTC Magazine

The VMEbus has become one of the most successful and long-lived buses in the history of embedded computing, extending a compatible infrastructure across 20 years and several generations of computing technology. The philosophy of VMEbus technology has allowed a large number of technology insertions—D64, MBLT, RACE++, StarFabric and now 2eSST, to name a few—while maintaining complete mechanical, electrical and software compatibility with all pre-existing legacy solutions.

This philosophy has allowed VMEbus system integrators to mix custom and off-the-shelf cards with the assurance that their investment in hardware and software would be protected as portions of the system migrated to newer technologies. It has also allowed incremental upgrades to systems after deployment, making VMEbus technology an excellent choice for defense and industrial applications with long product lifecycles.

Over the last several years, the need for bandwidth and scalability in high-performance applications has resulted in the development of several standards that extend the technology. Using the extensibility provided by the user-defined regions of P2 and P0, standards such as RACE++, SKYchannel, Myrinet and StarFabric added switched fabric interconnect to VME while maintaining compatibility with legacy VME cards. These standards used parallel connections between nodes due to the signal integrity limitations of the connectors. Because there were no open switched fabric protocols, each standard’s underlying technology tended to be controlled by one company, resulting in open standards but limited choices for users.

VXS Architecture

The next generation of scalable embedded computing solutions will be based on open interconnect standards such as PCI Express and Serial RapidIO. Because these standards are being widely adopted, the underlying technology is supported by multiple companies offering endpoints, switches, software and IP core solutions.

However, unlike parallel bus interfaces such as VME and PCI, new switched fabric interconnects are all based on high-speed serial links. Each serial link combines clock and data into a single differential pair, eliminating the need for low-skew layout even when multiple links are used between nodes. One 3.125 Gbit/s differential pair supports data throughput of 312.5 Mbytes/s using two pins. By comparison, a single parallel RACE++ port requires 41 pins to provide throughput of 267 Mbytes/s.

While the density advantages of high-speed serial links are obvious, the signal integrity limitations of the existing P2 and P0 connectors do not support the 2.5 and 3.125 Gbit/s connections used by PCI Express and Serial RapidIO. To support the next generation of interconnects, a new connector solution was required.

The VITA 41 VXS standard adds support for next-generation serial interconnects in a way that is consistent with the VMEbus philosophy of incremental evolution. First and foremost, VXS maintains complete mechanical and electrical compatibility with legacy VMEbus technology through the use of the same 6U form-factor and P1 / P2 DIN connectors. This allows a VXS-enabled system to support any existing VMEbus card that uses the traditional P1 and P2 connectors.

VXS defines two types of cards: payload cards and switch cards. Payload cards look a lot like legacy VMEbus cards. They have the traditional P1 and P2 connectors, standard VME64x with 2eSST, and a new higher-speed P0 connector with 8 full-duplex serial links providing up to 2.5 Gbits/s of throughput in each direction. Switch cards use higher density connectors and provide high-density interconnect between payload cards but do not support legacy VME connections through P1 and P2.

VXS-compatible backplanes can support any mix of payload and switch cards in a variety of topologies. VXS backplanes are completely passive, providing high-speed interconnect between cards but without active switching on the backplane itself. This offers an advantage over interconnects such as RACE++ and SKYchannel, which require active interlink modules mounted behind the backplane to provide the switching function.

VXS is inherently fabric agnostic, supporting a range of high-speed serial fabrics using the same pinout, connector and backplane. The fabric essentially becomes an agreement between the payload and switch cards in the system, allowing VXS infrastructure to be used for open standard fabrics such as PCI Express, Serial RapidIO, InfiniBand and Gigabit Ethernet, as well as application-specific interfaces.

One advantage of the VXS architecture is support for a range of topologies with common payload and switch card interfaces. Larger VXS systems will typically use redundant switch cards to implement a dual-star topology as shown in Figure 1(a). Smaller systems, with flexible payload cards, can implement switchless topologies to avoid the overhead of a separate switch card. In some systems, a mesh arrangement may make sense, with logical choices being 3 card meshes with x4 links, 5 card meshes with x2 links, or 9 card meshes with x1 links, shown in Figure 1(b). Another possible approach is a ring topology, shown in Figure 1(c). Another variant, shown in Figure 1(d), uses an asymmetric ring to maximize left-to-right bandwidth for pipelined signal or image processing applications.