Given the developments in programmable logic that have advanced the technology over recent years and months, and the continuing developments, the number and kinds of tricks you can teach your FPGA is growing by leaps and bounds. Within certain limitations (mostly of speed), you can use an FPGA to substitute for the traditional full-custom ASIC, achieving very significant savings in NRE costs, risk of failure, time-to-market and the ability to easily update protocols and other embedded logical functions without redoing a mask or returning to the fab.

You can use the smaller models for traditional “glue logic” functions. Some of the beefier varieties now support 32-bit soft processor cores—such as Altera’s NIOS or Xilinx’ MicroBlaze—that can be configured with a host of standard and custom peripherals. Others, like the Xilinx Virtex series and the QuickLogic QuickMIPS include hard-wired CPU cores that run familiar instruction sets.

You can use third-party tools like Matlab from The Mathworks to develop DSP functions and implement them in programmable logic. In many cases, you can simply put together pre-developed functionality in the form of IP blocks to emulate what earlier would have consisted of silicon devices. There are also tools that will convert C algorithms directly to programmable logic gates. All of these options have a definite place and usefulness.

The growing density and complexity of programmable logic devices is moving the development activity, and the tools that support it, to higher levels of abstraction. This should come as good news to embedded developers, many of whom equally share three aversions: writing assembly code, writing HDL code and root canal work.

It’s not that dropping down to these levels is never necessary in embedded development, but it is much more efficient and economical if a lot of the details involved with putting functionality into FPGAs have been “pre-sweated” so that one can focus on assembling the right mix of functionality on the device. This makes the use of FPGAs accessible to a wider number of developers, giving those with the specialized expertise of detailed logic design the opportunity to focus on creating functional IP that others can use.

Two popular ways of developing for FPGAs that take advantage of higher levels of abstraction are putting together blocks of IP and defining functionality in software—most often C—and then converting it to logic gates. These two approaches are not interchangeable in a practical sense. For one thing, an FPGA by its very nature as a hardware entity has the capability of implementing parallelism, in that functional logic blocks can often operate independently if they’re not dependent on each other. Software algorithms, on the other hand, are inherently sequential.

The “C to gates” approach makes the most sense when a long and often repeated sequence of instructions, or some specialized routine can be implemented more efficiently than allowed by the particular processor’s instruction set. The most popular of these are DSP algorithms, because DSP operations very often consist of a series of iterative steps that pass through a large amount of data.

Using the Matlab/Simulink tools from The MathWorks, developers are able to either develop new algorithms in Matlab or use pre-developed blocks in Simulink. Blocks developed with Matlab can be stitched together in Simulink or brought together with other legacy code and simulated using the ModelSim tool from Mentor Graphics. Both Xilinx and Altera have tools that can generate the HDL and the binaries to configure FPGAs.

For example, the Xilinx System Generator for DSP generates optimized VHDL code and IP cores along with HDL test bench and test vectors, constraint files for such things as I/O allocation and ModelSim script files for behavioral simulation. The System Generator is part of Xilinx’ ExtremeDSP offering, which includes IP cores, DSP classes, DSP boards and FPGAs.

Likewise, Altera’s DSP Builder utilizes Matlab and Simulink within Altera’s Quartus II design environment. Within that environment, DSP algorithms can be linked with existing Matlab functions and Simulink blocks as well as with Altera’s existing MegaCore IP blocks (Figure 1).

More recently, Xilinx has announced its Virtex4 family, which includes several versions tailored to general application areas such as DSP, logic-intensive and high-speed serial application domains. Now, they are announcing a tool set, the Integrated Software Environment (ISE) 6.3i Design Suite that includes wizards for helping configure the Virtex4 variants along with needed verification tools such as the PlanAhead floor plan tool.