RTC Magazine

AdvancedTCA is a blade architecture that provides tremendous flexibility for high bandwidth communication within a shelf, as befits its emphasis on telecom applications. An AdvancedTCA backplane is fabric-agnostic, so different communicating pairs of fabric interfaces on the blades may use the backplane links very differently. With this flexibility comes a challenge: ensuring that the fabric interfaces on each end of a backplane link are compatible with each other. For the simplest case of a fixed function interface on each end, a simple compatibility match is required. In the general case, each end of a link may be configurable (perhaps via dynamically loaded FPGAs) to support one of a range of fabric types; that possibility needs to be supported also.

In AdvancedTCA, this challenge is addressed by the E-Keying subsystem of platform management—the foundation management layer that inventories the Field Replaceable Units (FRUs) in the shelves of a system, monitors their basic health and manages their power, cooling and interconnect resources. PICMG has chosen to leverage the widely used Intelligent Platform Management Interface (IPMI) infrastructure, adding advanced extensions that address the special platform management needs of communication systems. PICMG 3.0, the AdvancedTCA specification, defines the necessary extensions to IPMI. Figure 1 shows the management-related logical elements of an example AdvancedTCA shelf.

Intelligent Platform Management in ATCA

AdvancedTCA brings with it some terminology that differs from traditional embedded computer architectures. For instance, “blades” are referred to as “boards”, and “shelf” replaces the term “chassis” that is traditional in some circles. An AdvancedTCA Shelf Manager communicates inside the shelf with IPM Controllers, each of which is responsible for local management of one or more Field Replaceable Units (FRUs), such as boards, fan trays or power entry modules.

Management communication within a shelf occurs primarily over the Intelligent Platform Management Bus (IPMB), which is implemented on a dual-redundant basis as IPMB-0 in AdvancedTCA. FRU Information (accessed via the IPM Controller responsible for each FRU) provides data about the FRU, including inventory information such as manufacturer and model identification. Shelf FRU Information provides similar information for the shelf, itself, including the integrated backplane.

The Shelf Manager has two main responsibilities. First, it manages/tracks the FRU population and common infrastructure of a shelf, especially the power, cooling and interconnect resources and their usage. Within the shelf, this management/tracking primarily occurs through interactions between the Shelf Manager and the IPM Controllers over IPMB-0. The other duty of the Shelf Manager is to enable the overall System Manager to join in that management/tracking through the System Manager Interface, which is typically implemented over Ethernet.

Electronic Keying in AdvancedTCA

The IPMC’s non-volatile storage includes FRU Information (with E-Keying data) for the board. Figure 2 shows the management aspects of an ATCA board that are relevant to E-Keying. The IPMC manages the point-to-point E-Keying controls for the Base, Fabric and Update Channel Interfaces that are implemented on a particular board. The board Payload, itself, manages E-Keying controls for its use of the Synchronization Clock Interface and Metallic Test buses. AdvancedTCA’s provisions for E-Keying these bused resources are very different from the point-to-point E-Keying provisions. The remainder of this article focuses on the point-to-point E-Keying architecture.

The first step in point-to-point (P2P) E-Keying happens when a shelf is first powered up. The Shelf Manager gets the backplane P2P connectivity data from the Shelf FRU Information. This data specifies the P2P interconnections that the backplane provides between specific slots and specific channels on each slot.

Next, for each board in the shelf (whether present at power up or added later), the Shelf Manager determines from board level FRU Information the P2P connections to the backplane that each board implements and the potential logical links to other boards that each of those connections can support. Each such link has a link descriptor that identifies:

• a P2P Interface on the backplane (Fabric, Base or Update Channel) and a channel number within that interface;
• the ports (or sets of differential signal pairs) on that channel that are involved in the link; and
• the link type (which identifies the governing PICMG 3.x subsidiary specification—say, PICMG 3.4 PCI Express—and selects among any variants defined by that specification).