RTC Magazine

The VITA 42 Switched Mezzanine Card (XMC) standards, not surprisingly, continue to gain traction. Today’s embedded applications demand more of their platform hardware than ever, particularly their I/O subsystems, and it has become a forgone conclusion that switched fabrics like those enabled by XMCs will play a prominent role in their success. The XMC standards, an evolutionary step in mezzanine technology, provide backward compatibility with legacy PMC modules while allowing PCI-bus products to integrate switched fabric architectures. The standards build on the existing PMC standards by adding switched fabric interconnects to the existing PCI bus interface.

Currently, drafts for XMC.1 (Parallel RIO), XMC.2 (Serial RIO), XMC.3 (PCI Express) and the base standard (XMC.0) are under review and being prepared for balloting and ultimately ANSI standardization. Once focused squarely on the high-performance embedded market, XMC has gone through several iterations of focused refinement and, as a result, shows every indication that it will tap additional markets. A case in point is the addition of a PCI Express “dot spec”, XMC.3, to provide backward compatibility with PCI plug-and-play systems. By mapping the PCI Express to this standard form-factor, XMCs will no doubt secure a place in one of PCI’s traditional strongholds: network equipment.

In fact, XMC’s potential in PCI-related markets is considered so strong that PICMG recently began collaboration with VITA to bring PCI Express to the PMC and Processor PMC standards. PICMG envisions a standard that supports all PICMG’s requirements for launching PCI Express on the ubiquitous PMC form-factor while heading off the need for a PICMG-specific standard. PICMG reasons that a single standard supported by both PICMG and VITA will minimize market fragmentation.

Another market-expanding addition to the XMC standards is the conduction-cooled option, which piggybacks off the VITA 20 Conduction Cooled PMC standard. Conduction-cooled modules are required for applications where convection cooling or forced air cooling are not appropriate. By offering this variant, XMCs should secure a market presence in one of VME’s traditional strongholds: high-performance defense systems operating in tight spaces.

Fabric Selection

While having three dot specs in the pipeline clearly shows the general direction of tomorrow’s XMC solutions, it also shows that fabric technologies are still in the sorting out stage. Early developers of XMCs and their ancillary building block components are initially adopting Parallel RapidIO (XMC.1) due to the on-chip interfaces available with Freescale’s 8540 and 8560 processors.

RapidIO is seen by many as a single technology that can satisfy a wide range of system-level interconnect requirements. Control and data plane functions can be implemented seamlessly. And equally important to network and telecom designers, the protocol delivers increased bandwidth with the added focus of improved reliability.

Parallel RapidIO goes a long way toward addressing many pressing needs in next-generation systems, but limitations inherent in parallel protocols will ultimately push vendors toward serial protocols such as Serial RapidIO (XMC.2) or PCI Express (XMC.3). Most notably, parallel architectures impose distance limits due to signal skew budgets. While signal skew is not an issue for short runs such as chip-to-chip circuits, longer circuits such as board-to-mezzanine or board-to-board in long backplanes or so-called box-to-box interconnects are greatly simplified with skew-tolerant serial protocols.

Applications requiring multiple chassis, such as many defense and industrial applications, stand to benefit from the added distances possible with serial protocols. And the use of serial fabrics can result in very low pin counts, an important design parameter for power- and pin-sensitive designs.

Serial RapidIO, the basis for XMC.2, provides an open standard interconnect designed from the ground up to meet the scalability, throughput and latency requirements of high-performance embedded computing, and also stands out as a logical migration path for vendors cutting their teeth with Parallel RapidIO. Serial RapidIO’s compatibility with standard FPGAs, its peer-to-peer communications model and compact size, which can fit within a small portion of a modern FPGA device, bode well for promoting XMC.2-compliant mezzanine and carrier products.

Serial RapidIO allows chip-to-chip and board-to-board communications at high-performance levels, and is expected to eventually scale to ten Gigabits per second per lane and beyond. Flow control extensions to the standards provide congestion control for medium-rate data plane applications using the RapidIO interconnect architecture. These end-to-end flow control extensions enable the development of RapidIO-based communications applications such as media gateways, radio network controllers (RNCs) and routers used in mobile networks.

PCI Express, Intel’s preferred successor to the PCI bus, can count on a large market presence fueled by the widespread availability of commodity components. Unlike its parallel bus predecessor, it is designed with its sights trained on markets beyond the desktop such as workstations and embedded devices. Intel expects PCI Express used in communications and embedded systems to benefit from lower costs, an enormous ecosystem and the widespread interoperability associated with the large volume market segments such as desktop and wireless products. As PCI Express components reach the market, XMC.3-compliant mezzanine and carrier cards will proliferate.

Since no clear favorite for serial fabric dominance has yet emerged and there is no guarantee that any single fabric will, most players developing XMCs and their carriers feel obliged to hedge their bets. Some are adopting multiple protocols for concurrent development. Others are following a single-fabric roadmap but with an eye toward a quick switch to another fabric should market forces dictate. Both strategies hope to secure advantageous positions if the demand for a particular protocol suddenly explodes.

Fabric Agnosticism

Commonality of connector, signal levels, and physical interface allows the development of modules and carriers that are fabric-agnostic, supporting either RapidIO, PCI Express, Advanced Switching or yet-to-be proposed interconnects within the framework of a single standard. Given the fuzzy picture facing fabric selection, the ability to design fabric-agnostic implementations is a major strength of the XMC standards.

A potential key enabler of fabric-agnostic XMC designs is the availability of large-scale FPGAs with integrated SerDes endpoints. Modern FPGA development tool chains allow designers to easily layer their IP and, by doing so, fabric-specific functions can operate separately and independently from higher-level application IP, and can change without impact on the application layer. By defining a uniform interface between the protocol layer and the application layer, the designer’s investment in user IP can be preserved over many fabric evolutions (Figure 1).

By limiting all protocol-specific logic to the FPGA protocol layer cores, careful board designs can take advantage of multi-protocol standards like VITA 42 (XMC) and VITA 41 (VXS) to implement various protocols on the same platform. The concept of fabric-agnostic designs is spreading due to the availability of large-scale FPGAs and to the recognition that tangible support for fabric agnosticism must arrive reasonably early in the move to fabric-centric architectures. In short, application designers are beginning to believe in agnosticism.

Pioneers in the area are already announcing support for a fabric-agnostic XMC built around a protocol layer for IP-to-IP pipelining. The protocol layer provides a simple streaming interface to user and third-party IP, and serves as the common user interface to fabric-specific IP cores such as PCI Express, Serial RapidIO and legacy protocols such as PCI and RACE++. The protocol layer defines a uniform interface between user IP and any of these fabric-specific cores.

An example implementation of a fabric-agnostic XMC design appears in Figure 2, which shows several protocol cores resident in an FPGA mounted on an XMC mezzanine card. As shown in the figure, the FPGA mounted on the XMC is loaded with three protocol cores. A PCI core moves data over PCI connectors J11 and J13. A front-end I/O core moves data over an external interface such as FPDP (VITA 17). A fabric core, such as a Serial RapidIO or PCI Express core, moves data over high-speed connector J15. User-developed IP can process data between any of these interfaces using the common core interface.

A sample use of User IP appears in Figure 3, clearly illustrating the integration role of the common core interface. In this case the user IP establishes a processing pipeline by connecting an off-the-shelf FFT core to a fabric on one side and the PCI bus on the other. Two fabric options are shown, PCI Express and Serial RapidIO. Improved third-party FFT cores could be inserted with no impact on application software or other FPGA IP, and pipelining other IP cores between the interconnect cores becomes straightforward.

Fabrics Gaining Traction

Switched fabric protocols implemented on XMC mezzanine cards, many using large scale FPGAs, are steadily gaining traction and will play a central role in next-generation systems. Three fabric switched protocol standards for XMCs are currently being drafted, and more are expected to appear in the future. These protocols are still in the sorting out stage, however, and will be for some time.

As a hedge against the uncertainty of which fabrics to support, IP layering lets the fabric-specific parts operate separately and independently from higher-level user IP. A common interface serving many protocols can then be defined, supporting the development of fabric-agnostic User IP.

By removing the fear from fabric selection, development of XMC carriers and mezzanines can move forward with less resistance. This and other developments, such as feature expansion to tap additional markets, are accelerating the pace of XMC product activity.

TEK Microsystems
Chelmsford, MA.
(978) 244-9200.
[www.tekmicro.com].