RTC Magazine

The VITA 42 Switched Mezzanine Card (XMC) standards, not surprisingly, continue to gain traction. Today’s embedded applications demand more of their platform hardware than ever, particularly their I/O subsystems, and it has become a forgone conclusion that switched fabrics like those enabled by XMCs will play a prominent role in their success. The XMC standards, an evolutionary step in mezzanine technology, provide backward compatibility with legacy PMC modules while allowing PCI-bus products to integrate switched fabric architectures. The standards build on the existing PMC standards by adding switched fabric interconnects to the existing PCI bus interface.

Currently, drafts for XMC.1 (Parallel RIO), XMC.2 (Serial RIO), XMC.3 (PCI Express) and the base standard (XMC.0) are under review and being prepared for balloting and ultimately ANSI standardization. Once focused squarely on the high-performance embedded market, XMC has gone through several iterations of focused refinement and, as a result, shows every indication that it will tap additional markets. A case in point is the addition of a PCI Express “dot spec”, XMC.3, to provide backward compatibility with PCI plug-and-play systems. By mapping the PCI Express to this standard form-factor, XMCs will no doubt secure a place in one of PCI’s traditional strongholds: network equipment.

In fact, XMC’s potential in PCI-related markets is considered so strong that PICMG recently began collaboration with VITA to bring PCI Express to the PMC and Processor PMC standards. PICMG envisions a standard that supports all PICMG’s requirements for launching PCI Express on the ubiquitous PMC form-factor while heading off the need for a PICMG-specific standard. PICMG reasons that a single standard supported by both PICMG and VITA will minimize market fragmentation.

Another market-expanding addition to the XMC standards is the conduction-cooled option, which piggybacks off the VITA 20 Conduction Cooled PMC standard. Conduction-cooled modules are required for applications where convection cooling or forced air cooling are not appropriate. By offering this variant, XMCs should secure a market presence in one of VME’s traditional strongholds: high-performance defense systems operating in tight spaces.

Fabric Selection

While having three dot specs in the pipeline clearly shows the general direction of tomorrow’s XMC solutions, it also shows that fabric technologies are still in the sorting out stage. Early developers of XMCs and their ancillary building block components are initially adopting Parallel RapidIO (XMC.1) due to the on-chip interfaces available with Freescale’s 8540 and 8560 processors.

RapidIO is seen by many as a single technology that can satisfy a wide range of system-level interconnect requirements. Control and data plane functions can be implemented seamlessly. And equally important to network and telecom designers, the protocol delivers increased bandwidth with the added focus of improved reliability.

Parallel RapidIO goes a long way toward addressing many pressing needs in next-generation systems, but limitations inherent in parallel protocols will ultimately push vendors toward serial protocols such as Serial RapidIO (XMC.2) or PCI Express (XMC.3). Most notably, parallel architectures impose distance limits due to signal skew budgets. While signal skew is not an issue for short runs such as chip-to-chip circuits, longer circuits such as board-to-mezzanine or board-to-board in long backplanes or so-called box-to-box interconnects are greatly simplified with skew-tolerant serial protocols.

Applications requiring multiple chassis, such as many defense and industrial applications, stand to benefit from the added distances possible with serial protocols. And the use of serial fabrics can result in very low pin counts, an important design parameter for power- and pin-sensitive designs.

Serial RapidIO, the basis for XMC.2, provides an open standard interconnect designed from the ground up to meet the scalability, throughput and latency requirements of high-performance embedded computing, and also stands out as a logical migration path for vendors cutting their teeth with Parallel RapidIO. Serial RapidIO’s compatibility with standard FPGAs, its peer-to-peer communications model and compact size, which can fit within a small portion of a modern FPGA device, bode well for promoting XMC.2-compliant mezzanine and carrier products.

Serial RapidIO allows chip-to-chip and board-to-board communications at high-performance levels, and is expected to eventually scale to ten Gigabits per second per lane and beyond. Flow control extensions to the standards provide congestion control for medium-rate data plane applications using the RapidIO interconnect architecture. These end-to-end flow control extensions enable the development of RapidIO-based communications applications such as media gateways, radio network controllers (RNCs) and routers used in mobile networks.