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Congatec Cooperates with Freescale to Expand Product Line with ARM Modules

Congatec has announced that it is collaborating with Freescale Semiconductor to expand its product portfolio with the addition of ARM technology. This will allow the company to offer products with extremely low power requirements in the future. As a first step in that direction, congatec is expanding its Qseven product family with i.MX processors from Freescale.

Until now, congatec has focused exclusively on x86-based COMs (Computer-on-Modules), which in the past only allowed a choice between Intel and AMD. As part of its new product strategy, the company now plans to extend its offerings to include Freescale and its ARM-based i.MX portfolio of products.

The COM concept integrates all generally available interfaces onto the computer module itself while any special interfaces are implemented on individually tailored carrier boards. In complete contrast, the majority of existing ARM processors come with specialized interfaces designed to suit dedicated applications. These cannot be used by COMs in a standard format and are therefore neither interchangeable nor scalable. However, the new generation of ARM processors focuses on standard PC interfaces such as USB and PCI Express and will therefore be ideally suited to COMs.

The Qseven standard was designed from the very beginning around modern interfaces. Its specification was updated in September 2010 (Revision 1.20) to enable the development of 100% compatible ARM-based modules. The features offered by modern ARM processors and the interface definitions of Qseven are a perfect match and require no additional I/Os. This allows the development of price/performance-optimized modules and also makes the modules suitable for a range of completely new applications—many of them related to mobile operation and deployment. The first products resulting from the Freescale collaboration are expected to be available by the middle of 2012.

Fujitsu Semiconductor Standardizes on Mentor Graphics HyperLynx Signal Integrity Technology

Mentor Graphics has announced that Fujitsu Semiconductor has standardized on the Mentor Graphics HyperLynx Signal Integrity technology as the company’s LSI-IC Packaging (PKG)-Printed Circuit Board (PCB) co-design tool for fast and accurate high-speed simulation and analysis. For today’s highly functional end-products, bus speeds are increasingly getting faster and the demand for noise timing-aware LSI-PKG-PCB co-design is increasing. Fujitsu Semiconductor adopted the HyperLynx product suite to address problems caused by high-speed signals throughout the design cycle, from early architectural stages through post-layout verification.

As memory bus speeds get faster, timing margins become more severe, impacting simultaneous switching noise and timing design. For good quality control and optimized performance, this affects the ICs, the packaging, and the printed boards. This includes traditional challenges such as signal crosstalk, over-shooting and under-shooting. Since the HyperLynx product is easy-to-use and provides an intuitive user interface, all members of the product development team (hardware engineers, PCB designers and signal integrity specialists) can use it, from pre-layout analysis and simulation to post-layout verification.

Complete P25 SDR Waveform Ported to Android Helps Migration of SDRs

Objective Interface Systems has announced that Communications Research Centre Canada (CRC) ported a complete APCO P25 waveform and Software Communications Architecture (SCA) radio system to a small form factor Android device in just one day with zero source code modifications using the ORBexpress communications software. This port by CRC of the P25 waveform to an Android device realizes the Joint Tactical Radio System (JTRS) program initiative to facilitate the migration of software-defined radios (SDRs) to smaller, commercial form factors to enable faster time to market and substantially lower development costs.

The Association of Public-Safety Communications Officials (APCO) Project 25 (P25) is a complex, public-safety waveform that federal, state/province and local public-safety agencies use in North America to enable communication with other agencies and mutual aid response teams in emergencies. The P25 waveform was designed to improve interoperability among civilian public-safety agencies. This port by CRC proves that public-safety radios can now easily adapt to new operating parameters—the real strength of SDR in a public-safety communications system. In addition, the success of this port makes it easier for military radios to communicate easily and seamlessly with public-safety radios during homeland security and other emergency situations. CRC’s port of the entire radio system, including a full core framework and a P25 waveform application, ran seamlessly while achieving long battery life on a dual-core ARM processor.

Advantech Partners with Silicom; Adds six Network Mezzanine Cards

Advantech has announced a partnership that will enable Advantech to integrate Silicom’s range of multi-port networking bypass adapters into their network appliance platforms. Initially, Advantech will offer six Intel NIC-based PCIe Network Mezzanine Cards (NMCs) with support for 1GbE fiber or copper bypass ports and 10GbE fiber bypass ports.

“More than ever, time to market, re-usability of software across platforms and total cost of ownership are key factors for success of our OEM customers. Network Equipment Manufacturers now can seamlessly combine the benefits of our modular and field replaceable network interfaces based on NMCs and Silicom’s unique and powerful bypass implementation,” stated Peter Marek, Director x86 Solutions for Advantech’s Networks and Communications Group. “Especially, customers using Silicom NICs on other platforms can now move to Advantech’s leading edge appliances without having to invest in, spend time on, or maintain software to accommodate different bypass schemes.”

Renesas Receives USB-IF Certification for USB 3.0-SATA3 Bridge System-on-Chip

Renesas has announced that its SuperSpeed USB (USB 3.0) SATA3 bridge system-on-chip (SoC), part number, µPD720230, has passed the certification testing by the USB Implementers Forum (USB-IF). Renesas also announced that AMD has tested and verified chipset compatibility with Renesas’ performance-enhancing UASP software for external storage devices.

USB 3.0 achieves data transfer speeds that are up to 10 times faster than the previous version of the standard, enabling more rapid and efficient transfers of data to and from external storage devices. Renesas has led the industry by introducing the world’s first USB 3.0 host controller in May 2009, and the company’s lineup of USB 3.0 host controllers has been broadly adopted by customers worldwide with total shipments already exceeding 450 million units.

A newly defined mass-storage class protocol, USB Attached SCSI Protocol (UASP) allows mass-storage devices to operate more efficiently, and therefore take advantage of the increased bandwidth available SuperSpeed Universal Serial Bus (USB 3.0) interface. In December 2009, Renesas released a UASP driver, followed by the launch of a USB 3.0-SATA3 bridge SoC (µPD720230) in August 2011, which was the world’s first USB 3.0-to-SATA3 bridge SoC that supports UASP.

Renesas is currently working with leading chipset manufacturers to ensure that its UASP software is compatible with their chipsets. The UASP driver runs not only on the Renesas µPD720200 USB 3.0 host controller and its follow-on products (µPD720200A, µPD720201 and µPD720202), but also on A70M and A75 AMD Fusion Controller Hubs and its future products.

Test Event for IPv6 at the Customer Edge and Beyond

The University of New Hampshire InterOperability Laboratory (UNH-IOL), an independent provider of broad-based testing and standards conformance services for the networking industry, has announced it has seen an increase in the number of customer edge (CE) routers that are capable of being deployed in IPv6 networks, as evidenced by results of the lab’s recent IPv6 CE Router Interoperability Test Event. In addition to hosting IPv6 interoperability test events, the UNH-IOL helps member companies cost effectively speed IPv6 broadband deployments through a variety of educational materials, including a recently released IPv6 CE whitepaper and a newly launched YouTube video series.

The UNH-IOL’s third IPv6 CE Router Interoperability Test Event, which took place last month, brought together a total of eight operators and CE Router vendors to prepare for the delivery of reliable, uninterrupted Internet service to new and existing customers using IPv6, and to enable end-user connectivity by ensuring IPv6 readiness in home or small office networking environments. Participants included Actiontec, Broadcom, Cisco, D-Link, Lantiq, Motorola Mobility and Time Warner. In addition to verifying that CE routers are ready to be deployed in IPv6 networks, the test event proved support of transition mechanisms, such as 6rd, in some CE Routers, which is needed to maintain connectivity for subscribers when networks are not dual-stack (both IPv4 and IPv6). When making recommendations or purchasing decisions, operators and consumers alike may refer to the CE Router Tested List, which will be updated as vendors continue to test IPv6 CE devices at the UNH-IOL, to find out which routers will work in homes and small offices using IPv6.

Microsemi Unveils SmartFusion cSoC and FPGA Private Label Program

Microsemi has unveiled a private labeling program for its SmartFusion customizable system-on-chip (cSoC) and its broad portfolio of flash and antifuse-based FPGA solutions. Key program features include:

• Custom Marking: Devices are marked with the customer’s logo and part number.
• Factory Programming: Microsemi programs all devices, alleviating the need for customers to build in-house programming capabilities and infrastructure.
• Licensing: Microsemi’s Smart-Fusion cSoCs include a licensed, hard ARM Cortex-M3 processor, eliminating the need to obtain a separate ARM license.
• Fabless Model: Private labeling eliminates the time and costs associated with establishing and managing a chip manufacturing infrastructure.
• No Tooling Charges: No costly non-recurring engineering charges associated with Microsemi’s off-the-shelf SmartFusion cSoCs and FPGAs.

More than a dozen companies are already leveraging Microsemi’s flash-based, highly flexible architectures to quickly deliver tailored solutions to customers, quickly and cost-effectively.

Microsemi’s SmartFusion cSoCs are devices that integrate an FPGA, a complete microcontroller built around a hard ARM Cortex-M3 processor and programmable analog, enabling full customization and IP protection. Based on Microsemi’s proprietary flash process, SmartFusion devices are intended for hardware and embedded designers who need a highly integrated SoC that provides more flexibility than traditional fixed-function microcontrollers, and significantly reduces the cost of soft processor cores on traditional FPGAs.