OpenVPX System Specification Ratified by VSO
VITA has announced that the VITA Standards Organization (VSO) working group responsible for the VITA 65 OpenVPX System Specification has ratified the specification. The specification now meets the final criteria enabling balloting to proceed for ANSI ratification.
The VITA 65 working group received the original body of work from the OpenVPX Industry Working Group in October of 2009. Since then, the VITA 65 working group has been resolving the last outstanding comments received during the balloting process. At the January VSO meeting, the required number of approvals was achieved, officially recognizing the specification as ratified by the VSO. Special acknowledgement should be made to Curtiss-Wright Controls Embedded Computing’s Pete Jha, chairperson of the VITA 65 working group, and Mercury Computer Systems’ Greg Rocco, lead editor of the VITA 65 working group, for their tireless contribution to the timely ratification process, and congratulations to the rest of the working group members.
VPX is a broadly defined technology utilizing the latest in a variety of switched fabric technologies in 3U and 6U format modules. OpenVPX is the architecture framework that defines system-level VPX interoperability for multivendor, multimodule, integrated system environments. The OpenVPX framework delineates clear interoperability points necessary for integrating module to module, module to backplane, and chassis. OpenVPX recommends but does not specify development systems to assist in VPX system evaluation, prototyping and development. OpenVPX will evolve and incorporate new fabric, connector and system technology as new standards are defined.
The working group will now submit the specification to a larger body of interested parties for balloting as part of the process to gain ANSI ratification. This process is expected to take 2-3 months, after which time the specification will be available to designers in the industry.
Xilinx Picks 28nm Process to Accelerate Platforms
Xilinx has announced the foundation for a next generation of programmable platforms to address what it calls the “Programmable Imperative.” That refers to today’s numerous trends—the exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing. These, Xilinx maintains, are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs.
Xilinx has chosen to maximize the value of the 28nm technology node by choosing a high-performance, low-power process technology, a common scalable architecture across product ranges, and tool innovations so customers will have FPGAs that deliver the ASIC-class capabilities they need to meet their cost and power budgets, while improving their productivity through easy design migration and IP reuse.
At the same time, power management and the impact it has on system costs and performance is a paramount concern to today’s electrical system designers and manufacturers. Compared to the standard high-performance process, the high-performance, low-power process delivers FPGAs that are 50% lower in static power. Meanwhile, next-generation development tools reduce dynamic power as much as 20% through innovative clock management. Enhancements made to Xilinx’s partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33%.
To address system performance bottlenecks caused at the interconnect level, Xilinx will provide the industry’s highest performance interfaces to support customers who need high-bandwidth chip-to-chip, board-to-board and box-to-box connections. This is of critical importance as customers increasingly look to FPGAs to become a major, if not central, component of their systems, and helps define how the next generation of FPGAs will enable customers to build their systems when ASIC and ASSP options are unavailable.
SFF-SIG Adopts CoreExpress Spec to Strengthen PCIe 2.0-Ready COM Portfolio
The Small Form Factor Special Interest Group (SFF-SIG), a collaboration of suppliers of embedded component, board and system technologies, today announced the adoption and release of the CoreExpress Specification revision 2.1. CoreExpress was originally developed as a proprietary standard by Lippert Embedded Computers GmbH. Under the terms of an agreement between SFF-SIG and Lippert, the entire embedded community will now be able to develop CoreExpress modules and applications without regard to confidentiality and without royalties of any kind. Use of the CoreExpress logo will require membership in SFF-SIG.
The newly released version of the specification contains a number of enhancements proposed by SFF-SIG members during the evaluation process. These include the support of the emerging DisplayPort interface and the addition of sufficient reserve pins to enable upward compatible support for USB 3.0 in the future. The new version is upward compatible from the current CoreExpress 2.0 version previously published by Lippert.
CoreExpress uses a single connector baseboard interface, eliminating the registration problems frequently found with two-connector Computer-on-Module products. Fully digital to reduce system noise and EMI, CoreExpress is the smallest x86 computer-on-module in the market, measuring a mere 58 x 65 mm. With dedicated interface pins for optional CAN bus support, CoreExpress ushers in a new era of “application COMs” tailored for vertical markets.
Three characteristics establish the CoreExpress Specification as the first of a new generation of Computer-on-Modules. First, the connector used by CoreExpress modules has been confirmed to operate at the speeds required for PCI Express Generation 2. Secondly, the specification contains an option to configure the SDVO interface pins for the new DisplayPort interface. Third, sufficient reserved pins are included in the definition to enable inclusion of at least two USB 3.0 ports in a future release of the specification.
The CoreExpress baseboard interface includes PCI Express (configured as one x4 lane or four x1 lanes), RGMII Ethernet, 2 SATA ports, 1 CAN port, 8 USB 2.0 ports (one of which may be configured as a client), LPC bus, SM bus, High Definition Audio, SDVO (multiplexed with Display Port), 24-bit LVDS flat panel interface, backlight control and an SD/SDIO/MMC 8-bit interface. The CoreExpress Specification is available for download from the SFF-SIG Web site at www.sff-sig.org. CoreExpress modules are available today from Lippert Embedded Computers.
OpenSAF in Commercial Deployment
The OpenSAF Foundation, the not-for-profit organization supporting the Open Service Availability Forum (OpenSAF) open source high-availability middleware projects, has announced that Ericsson has deployed the OpenSAF technology in carrier networks. This represents the first public statement by a major equipment manufacturer on commercial adoption, development and deployment of OpenSAF.
Since its launch in January 2008, the OpenSAF community has released two major versions of the code base, incorporating over 200 significant contributions, with hundreds of downloads of the releases. The number of developers and users is growing continuously and the high-availability software and systems expertise within the project is extremely high, resulting in a level of quality required to deploy in carrier networks.
“Ericsson’s commitment to OpenSAF in their commercial products is significant” said Alan Meyer, president of the OpenSAF Foundation. “Multiple other companies are also contributing to the OpenSAF code base as well as using OpenSAF for commercial developments. Like Ericsson, many of these applications are in communication networks, and we anticipate further public success stories in the future.”
Open-Silicon and Virage Logic Partner for Low-Power SoC Design
Open-Silicon and Virage Logic have announced a partnership agreement to provide customers with comprehensive design solutions including access to Virage Logic’s extensive Physical and advanced Interface intellectual property (IP) portfolio. In particular, as more and more customers develop energy-efficient devices, Virage Logic’s low-power IP combined with Open-Silicon’s lower-power design technology enable the development of significantly lower power silicon.
The partnership presents a well-aligned technology offering. Virage Logic, a leader in low-power semiconductor IP technology, uses several advanced power management features within the SiWare Memory compilers and SiWare Logic libraries that enable customers to dramatically reduce leakage current while maximizing performance. Open-Silicon’s VariMAX back biasing technology similarly works with Virage Logic’s tapless SiWare Logic standard cell libraries to reduce leakage for the IC’s logic. By changing the amount of bias used on individual chips, VariMAX effectively tunes the silicon for optimum power and thereby boosts production yields. This latest collaboration builds on a recently announced co-developed test chip with working silicon running at 1.1 GHz that was achieved using Open-Silicon’s patented CoreMAX performance enhancement technology and Virage Logic’s advanced SiWare Memory compilers.
“As power management and efficiency are becoming increasingly critical in a multiplicity of products and technologies, our collaboration with Open-Silicon underscores how we are working with our design ecosystem partners to help SoC designers address these challenges,” said Dr. Alex Shubat, president and CEO of Virage Logic. “Open-Silicon’s MAX Technologies working in conjunction with Virage Logic’s extensive semiconductor IP portfolio enables our mutual customers to address a broad range of SoC design requirements.”
Mentor Graphics Acquires Virtual Garage from Freescale
Mentor Graphics Corporation has announced the acquisition of the Virtual Garage product line from Freescale. Virtual Garage is a software suite that addresses two important topics within the design and management of automotive electrical and electronic systems: the trade-off between value-of-variety and cost-of-complexity caused by optional electronic content; and provision of vehicle-specific design data, such as dynamic electrical schematics, on demand to service networks.
Both topics carry significant profitability implications. Virtual Garage is seen as highly complementary to Mentor’s CHS software for electrical systems design and wire harness engineering. Virtual Garage expands Mentor’s scope both upstream into product planning, where decisions about product configuration complexity significantly impact long-term costs, and downstream into the key area of online service documentation for dealer networks.
The Virtual Garage products add significant value across the supply chain. Mentor has acquired the relevant intellectual assets and the key architects of the solutions. Mentor also acquired one key commercial contract under the acquisition. Following this technology acquisition, Virtual Garage will be incorporated into Mentor’s automotive industry product portfolio. Virtual Garage will also be featured in several sessions at the upcoming IESF conference in Detroit on March 18, 2010.
ZigBee Alliance Begins Certification for Sub-1 GHz Platforms
The ZigBee Alliance has announced it is now offering certification for ZigBee platforms designed to operate in the regional sub-1 GHz unlicensed frequencies. More semiconductor manufacturers and Alliance members are seeing a growing market for a range of ZigBee device options using the ZigBee specification. The Alliance recently completed its first series of multi-vendor interoperability tests for sub-1 GHz platforms. These platforms will become the Golden Units against which all other platforms seeking certification will be compared. They offer the same underlying functions and robust capabilities as existing ZigBee-compliant platforms operating at 2.4 GHz.
Atmel Corporation, Exegin Technologies and ZMDI are leading this effort in conjunction with ZigBee Alliance’s accredited test houses, National Technical Systems, TRaC Global and TÜV Rheinland.
The ZigBee specification has always supported sub-1 GHz platforms, but offering certification of platforms built to the specification requires at least three independent implementations for initial testing and validation. This rigorous certification requirement ensures that Alliance members only deliver interoperable solutions to the marketplace.
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