By: Colin McCracken, Small Form Factor SIG
New I/O perspective challenges conventional wisdom about stackable architectures.
An amazing thing happens when engineers and product marketers talk directly to customers and end users. This direct, unfiltered interchange provides not only “what” is required, but “how” and “why” specific choices are made. Applying this principle to the small form-factor computer arena provides a fresh round of customer data, which can be used to create standards with cohesion, consistency and stability over a 10-year-plus horizon.
Talking to users about their evolving small form-factor embedded computing needs is leading to a new set of governing standards that can move this fragmented market forward. Coordination and cooperation in what has become the fastest growing area of the embedded computing market can replace the lack of standardization and diffusion common today.
Decades of CPU-Driven Standards
For small form-factor SBCs, board-to-board interfaces have been nothing more than repackaged PC chipset buses for decades. Going forward, these CPU-centric notions must be re-examined, as pressures to bring more functionality into smaller spaces requires flexibility and leaves no room for inefficiency.
When looking at new processors or chipsets, once again the tendency is to bring their highest-speed buses to off-board expansion connectors, with the belief that anything slower can be created with bridge chips or FPGAs. After all, PCI Express is newer than the PCI Bus, which was newer than the ISA Bus. Imagine the possibilities with a PCI Express x16 interface! Now imagine the overhead and waste in this when running relays that operate traffic signal lights if only a x16 PCI Express interface is available.
It is quite easy to examine the current chipsets on the market and create a new interface standard that showcases the highest bandwidth bus. That is essentially how most previous board-to-board interfaces were defined. This approach automatically dictates a particular CPU architecture in a self-fulfilling prophecy. Considering PCI Express high bandwidth versus the low-speed I/O and 100-600 MHz processors used broadly in today’s embedded market, the big question is whether or not the I/O community can drink from a fire hose to supply many garden-variety peripherals of the future.
Power to the People
For the majority of system manufacturers and integrators, what their equipment does and how it operates is all about the application, hardware and software. The Small Form Factor Special Interest Group (SFF-SIG), a new industry collaboration of many types of suppliers, including component vendors, board vendors, power supply and enclosure designers, wants to give system manufacturers a voice regarding the standards that drive the embedded computers they will purchase in the future.
The SIG members have been out talking to embedded systems designers during the last 6 months. These customers are system OEMs who rely upon off-the-shelf embedded computer systems and boards for long-lived applications. The design alternatives of either proprietary (single-vendor) non-standard solutions or full custom designs are plagued with vendor risk and alternative sourcing issues. The open market has always thrived on choice, so it is appropriate to query customer needs and then create useful, multi-sourced standards from their input.
With all of the “legacy free” hype in the market, the members were a bit surprised to learn that in many cases, the concern was not about how many Gigabytes per second will need to flow across the board-to-board interfaces, but rather how easy it needs to be to continue to attach low-speed input and output devices in the future. It appears that rumors of the death of legacy peripherals and the ISA Bus have been greatly exaggerated. Some of the feedback we received is depicted in Figures 1 and 2. Figure 1 represents an aggregation of customer feedback regarding where the requirements for the majority of systems fall with regard to processor power and speed and the capabilities of the I/O.
The venerable serial port has vanished from desktop motherboards. Many embedded processor boards continue to provide these thanks to legacy serial and super I/O devices. Whether synchronous or asynchronous, serial ports are mainstream in embedded systems, both as external DB9 connectors and as cabled board-to-board interfaces. Medical, industrial, point-of-sale and portable devices all require support for serial peripherals. Bar code scanners, cash drawers, keypads and low-speed wireless converters are just a few examples.
Customers have stated they will be asking for serial ports for years to come. Sustainability of their application, software, hardware and cabling is built around using them. Fortunately, the Low Pin Count (LPC) Bus Specification, originated by Intel to reduce the number of pins necessary to implement the ISA interface, has led to many long lifecycle serial components that are functionally identical to previous ISA bus-based serial ports. For customers who can use plug-and-play automatic resource assignment and modern operating systems, PCI Express-based UARTs are starting to appear on the market. USB-to-serial converters are also readily available.
A/D, D/A and Other Low-Speed I/O
Data acquisition and process monitoring applications involve frequent sampling, but compared to GHz processors and Gigabyte per second interfaces, their data rates are quite slow. Data sampling can occur from mere hundreds to sometimes millions of times per second. This is because the processes being measured simply don’t change very rapidly or the A/D conversion itself has only modest throughput. Sample data storage can also become large and unnecessarily costly at higher rates.
Control and sensor applications, including turning on and off signals, lights, engaging latches, triggering events and energizing relays, require even less bandwidth.
Low-speed, two-wire buses, or multiplexed address-data-control buses with speeds from several hundred Kilohertz to no more than 33 MHz, can provide space-efficient, easy interface solutions for embedded designers. Interfacing to PCI Express by contrast would be a poor use of space and cost, and possibly could complicate device drivers.
Customers are asking for pluggable/removable devices for OS loading during boot, for data collection, even for diagnostics. Embedded systems typically require a mounting structure for removable devices. Consumer and Enterprise dongle-style solutions would be prone to dislodging, accidental bumping and overall reliability concerns.
There are two better solutions for embedded. One is to create a mounting bracket for the device, whether internal or external, with a short cable providing strain relief. Another would involve multiple USB ports on a board-to-board expansion interface, so that removable devices would have a mounting scheme on a printed circuit board expansion card. With USB, the rule of thumb is “more ports are better.” With 6, 8, or even 10 USB ports, laptop-derived chipsets have more than enough for embedded usage. Since only two differential pair pins are needed per port, plus over-current signals, SBCs can bring some ports to pin headers, some to PC-style connectors, and/or some to an expansion interface for flexible coverage of many uses. In Figure 2 we see the above points summarized in a consolidation of customer feedback regarding the I/O requirements of a system without regard to the processor architecture.
PCI peripherals have already moved to PCI Express in the desktop/notebook market. These will easily follow suit in the embedded market. PCI Express is a serial interconnect that is much more space efficient on small form-factor boards while offering 2.5 times the performance of legacy parallel PCI. PCI Express retains software and driver compatibility to parallel PCI, enhancing throughput to devices in a straightforward hardware migration without adversely affecting application software.
As PCI has already given way to PCI Express in the desktop PC market, a similar trend is already occurring in the embedded SBC market. 10/100 Megabit PCI Ethernet has been replaced with Gigabit Ethernet controllers on PCI Express x1 (“by one”) links on many new embedded systems. IEEE 1394 FireWire is moving to FireWire 800 (1394a) using PCI Express controllers. Wi-Fi (802.11) using mini-PCI will soon migrate to a standard mini-PCI Express socket as well.
Other existing uses for PCI like frame grabbers, PC Cards (32-bit PCMCIA cards) and a second video controller are moving as well. Frame grabber chips can be implemented with standard silicon as well as programmable devices (FPGAs) on PCI Express. The PCMCIA organization has successfully launched ExpressCard, which uses both PCI Express and USB, in the consumer/commercial space. Embedded is not far behind. Many chipsets now have integrated graphics controllers with two rendering pipes, which eliminate the need for an external controller in all but the highest-end applications.
New standards are needed soon to quickly complete this transition in the embedded market, so that bulky PCI connectors can be replaced on small SBCs where real estate is at a premium. PCI Express requires only 5 pins per x1 link.
From the chipset point of view, x16 PCI Express graphics are mainstream now, and come with two de facto standard interfaces: The vertical desktop x16 slot and the MXM interface originated by nVIDIA for low-profile applications. Looking at these examples, and with the cost and complexity of designing 50+ watt graphics cards, a new connector definition just for the embedded SBC market is simply not warranted. At these levels, power delivery, power density and thermal management can easily overwhelm every other system cost and design constraint.
SIG members’ customer feedback also reflected that chipset integrated graphics have improved to the point where they are suitable for nearly all embedded-class applications. The use of short-lifecycle consumer graphics chips and boards is relegated to gaming, signage and imaging applications that have solutions in place already.
Storage interfaces are more stable, but the transition from PATA (EIDE) to SATA is being dragged out over quite a long time horizon. Embedded engineers want to continue to use rugged pin headers (2 mm 44-pin and 0.1” 40-pin) for IDE, as well as the standard, space-sensitive SATA connectors directly off the motherboard, rather than putting any of these signals through board-to-board expansion connectors. These peripherals are ultimately cabled anyway, so consuming precious and comparatively expensive expansion connector pins does not make sense.
Solid-state storage continues to be requested for some of the most rugged and highest reliability applications. System OEMs are asking for long-term availability from embedded suppliers, along with high data integrity over extended read-write cycles, and stable, consistent firmware, rather than consumer-grade media that targets digital cameras.
Revisiting the CPU Core
For years, designers of embedded systems have been providing solid, consistent feedback to chip and board suppliers asking for a few simple requirements, as summarized in Table 1.
In the not so distant past, we have seen warmed over processors and chipsets, power hungry designs with onerous cooling requirements, board space requirements that compete with the original PC motherboard in size, a lack of small chip packages to support small form-factor boards, and a host of new product introductions and end-of-life notices on processors and chipsets with little regard to embedded product lifecycles.
Don’t despair; there is hope on the horizon. After a long hiatus from true embedded CPUs and chipsets, the revived Mobility and new Ultra Mobility product categories are driving useful, small, low-power, mid-performance processors and chipsets into the market. The lowest power and smallest package entries will be available starting this year, and ready for the mainstream by next year. Chip vendors are finally listening in that regard.
These ultra-small, very low-power chipsets include only a few legacy interfaces in favor of more modern buses like PCI Express, USB and SATA. Standards groups are left to make the best use of the features included in these chipset so that I/O and ease of use requirements can be met to satisfy the systems discussed.
If a suitable mix of moderate and fast chipset interfaces are chosen, the door can be wide open for easy peripheral connectivity, and even cross-architecture (x86, RISC, MIPS, etc.) participation in the next generation of small form-factor SBC standards. SFF member discussions with customers over the last six months have yielded a fresh, enlightened user perspective and replaced outdated notions as the approach to develop new standards.
Successful products combine an understanding of customer needs with innovative implementations, so why shouldn’t small form-factor PC standards be created the same way? The Small Form Factor SIG is determined to make this happen, at last. OEMs and vendors who share this I/Oand application perspective are invited to help create the badly needed specifications by joining this forward-thinking, inclusive trade group.
Small Form Factor SIG
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