Despite the advantages PCI Express offers as a standard protocol, it also offers
a number of challenges for the developer. As with any new protocol, designers
will have to design without the benefit of previous experience. For those designers
that are migrating to a high-speed forum from PCI or PCI-X, the complexities
will be quite demanding.
A high-speed link requires significant high-speed analog design expertise. At
data rates of over 1 Gbit/s the I/O buffer design requires significant changes,
and board layout techniques become crucial. Clock data recovery (CDR) circuitry
now also becomes extremely important. In addition to the analog considerations,
the digital logic required to process data is very different at high speeds. Encoding
schemes and compensation logic make the physical layer quite different from those
used with lower speed protocols. The PCI Express specification sets the requirements
for interoperability but is lenient in method of implementation. This freedom
allows the design to have the optimal implementation for the system, but also
requires that the designer have extensive knowledge of implementation techniques.
The design challenges associated with implementing this new and complex protocol
will directly affect time-to-market. Given the rapid adoption of the protocol
it is imperative to have products on the market as soon as possible. However,
most companies that were not directly involved with the standardization of the
protocol will have a much steeper learning curve, thereby creating an unnecessary
delay in product availability.
The FPGA Opportunity
FPGA devices offer a solution to many of the challenges facing new PCI Express
designers. The design cycle times for FPGA devices offer an inherent advantage
given that design iterations are much quicker. This is especially true since the
tool flow enables large scale designs to be implemented very effectively in FPGA
logic. Overall, the reduced time-to-market of a design is one of the prime advantages
an FPGA can offer.
FPGA devices also have built-in high-speed transceiver logic blocks that are designed
to support data rates beyond the 2.5 Gbits/s required for PCI Express. One of
the main advantages for using the dedicated transceiver blocks is that they have
been tested specifically for PCI Express by FPGA vendors. FPGA devices have also
been tested through compliance workshops and plug-in fests hosted by the PCI-SIG.
Given the analog design challenges that arise when designing for PCI Express,
FPGA devices offer the ability to use analog circuitry proven interoperability
There are defined methods of testing PCI Express layers regulated by the PCI-SIG
that provide easy proof-of-concept scenarios with FPGA devices. Since most industry
PCI Express implementations have been tested at formal compliance workshops, FPGA
devices offer a unique opportunity to ensure compatibility before designs even
Beyond the physical layer, the data link and transaction layers can also be implemented
in FPGA logic. The PCI Express specification details the requirements but leaves
much of the implementation up to the user. For the designer who would like the
quickest proven implementation in an FPGA, it is possible to purchase intellectual
property (IP) that has already been optimized for FPGA architectures. FPGA vendors
have worked to incorporate a full PCI Express solution that includes the transaction,
data link and physical layers.
high-speed transceiver can be used in the physical layer and IP can be used
for the transaction, data link and part of the physical layer. This allows the
designer to focus on the software implementation and worry only about the interface
to PCI Express. Existing PCI-X and PCI systems can be integrated to PCI Express
with minimal effort by using the IP and the built-in high-speed transceivers
Another main benefit of FPGA devices is reconfigurability. By the nature of
FPGA devices, designs can be instantly modified to allow for design changes
and potentially implement completely different systems. This works to reduce
design cycle times and simplifies making changes to designs that require it.
These qualities permit completely different PCI Express interfaces if desired.
Such flexible systems make it easy to change core PCI Express features including
number of channels and changing virtual channels. The priority of data packets
can be changed for a powerful method of adaptability. Analog features can also
be changed to aid in board layout. FPGA I/O buffers have the ability to change
voltage levels, de-emphasis and receive equalization. De-emphasis and receive
equalization are two extremely important features for board design and these parameters
can be changed dynamically without requiring device reconfiguration.
PCI Express components can be categorized as end-points, switches, PCI Express-to-PCI
bridges and root complexes. Each of these components has a different function
and can use FPGA devices in different ways. FPGA devices can be used for any
of the components but are more applicable in some cases than others. When designing
for a given system it is important to keep in mind the requirements for each
component to ensure a seamless interface for the whole system. FPGA devices
can be extremely useful as components for an efficient system (Figure 2).
End-points interface to switches and root complexes and are the most obvious fit
for FPGA devices. End-points have different functions and need to have some additional
resources to interact with the PCI Express fabric. The end-point application can
be implemented in the FPGA device and the high-speed transceivers can be used
for PCI Express communication. This allows designers to implement the actual end-point
application in an FPGA device and make use of the PCI Express-ready features.
End-points are the only PCI Express component that is unlikely to be PCI Express-specific.
End-points will need to serve the purpose of the component, while communicating
with other PCI Express components. As such, the flexibility of an FPGA will need
to be appropriate for the specific component, such as a SCSI or Ethernet controller.
Current PCI Express IP supports end-point applications and can easily be configured
to serve the purpose.
A switch is a PCI Express-specific component used for the purpose of “bridging”
multiple PCI Express devices. Switches will have upstream and downstream ports
that function to send information. FPGA devices are well-suited to these applications
for implementing upstream and downstream links. Switches are extremely easy to
implement on FPGA devices and IP can be used to quickly do so. System requirement
changes and data packet priority changes can also easily be implemented since
the FPGA is reconfigurable.
One component that is very well-suited for FPGA devices is a PCI Express-to-PCI
bridge. FPGA devices have been used extensively in PCI and PCI-X systems for many
years with interfaces that have been robustly tested. FPGA devices are particularly
appropriate for multiple I/O standards across many different data rates. Information
can move from PCI Express fabrics to PCI or PCI-X systems by the user’s
specification and IP is available for all these protocols to facilitate the process.
FPGA devices can be used for root complexes in a PCI Express fabric but will more
likely be implemented in ASICs. Nonetheless, there is IP that supports this structure
and allows the designer to configure the root complex to perform the required
FPGA devices can be used in multiple ways to support PCI Express. The designer
can choose to implement all or part of the protocol in an FPGA. If the full protocol
is implemented, the high-speed transceiver blocks will be used in addition to
the FPGA logic. In case the designer chooses to use another chip to implement
the physical layer, the FPGA can be used for the data link and transaction layers.
There are transceiver chips available that interface to the Intel PHY Interface
for PCI Express (PIPE) specification that can be combined with a low-cost FPGA
for a potential low-cost solution.
If the full protocol is implemented in an FPGA, the high-speed transceiver blocks
support physical layer characteristics of the PCI Express protocol. The full physical
layer would be implemented in a combination of the dedicated high-speed transceiver
blocks and the FPGA logic. The data link layer and the transaction layer would
be fully implemented in FPGA logic. The designer can choose whether or not to
fully design the layers or purchase IP to implement them.
The high-speed transceiver blocks will run at 2.5 Gbits/s as required by the PCI
Express protocol. It also has dedicated CDR circuitry that robustly extracts a
clock from the data. The 8B/10B encoding scheme is required in order to help with
clock recovery. The number of channels can accommodate most common link requirements.
The PCI Express specification has requirements for electrical characteristics
to ensure proper data transmission. The differential voltage is 1V with -3.5
dB de-emphasis required. This requirement is met with FPGA devices and the differential
voltage and de-emphasis can be dynamically changed in a lab environment to assist
with debugging boards (Figure 3). Receive channels also have equalization that
can dynamically be adjusted to accommodate for high frequency losses on the
The PCI Express specification also requires spread spectrum clocking (SSC).
FPGA devices can utilize a clock modulated by +0% to -0.5% and meets all the
SSC requirements without any special considerations. SSC is growing increasingly
important in most PCI Express systems. During implementation the designer has
to be able to control transceiver features including those mentioned above in
order to best meet specific system requirements.
FPGA devices offer a unique opportunity for designers to quickly and cheaply
implement PCI Express components without the long timeframe required when new
protocols come onto the market. For designers entering a high-speed forum for
the first time, the dedicated high-speed transceiver blocks embedded in FPGA
devices allow for a safe method of implementation. FPGA devices have been proven
in PCI Express compliance workshops and are being used in numerous PCI Express
applications. PCI Express promises to be the protocol of choice for systems
in the next generation, and being able to start designing quickly for PCI Express
is essential for today’s marketplace.
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